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![Simon Glass](/assets/img/avatar_default.png)
At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
630 lines
16 KiB
C
630 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017-2020 NXP
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
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* Layerscape PCIe driver
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*/
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#include <common.h>
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#include <dm.h>
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#include <init.h>
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#include <log.h>
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#include <pci.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/io.h>
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#include <errno.h>
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#ifdef CONFIG_OF_BOARD_SETUP
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#include <linux/libfdt.h>
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#include <fdt_support.h>
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#ifdef CONFIG_ARM
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#include <asm/arch/clock.h>
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#endif
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#include <malloc.h>
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#include <env.h>
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#include "pcie_layerscape.h"
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#include "pcie_layerscape_fixup_common.h"
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static int fdt_pcie_get_nodeoffset(void *blob, struct ls_pcie_rc *pcie_rc)
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{
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int nodeoffset;
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uint svr;
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char *compat = NULL;
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/* find pci controller node */
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nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
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pcie_rc->dbi_res.start);
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if (nodeoffset < 0) {
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#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
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svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
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if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
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svr == SVR_LS2048A || svr == SVR_LS2044A ||
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svr == SVR_LS2081A || svr == SVR_LS2041A)
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compat = "fsl,ls2088a-pcie";
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else
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compat = CONFIG_FSL_PCIE_COMPAT;
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nodeoffset =
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fdt_node_offset_by_compat_reg(blob, compat,
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pcie_rc->dbi_res.start);
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#endif
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}
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return nodeoffset;
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}
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#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
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/*
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* Return next available LUT index.
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*/
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static int ls_pcie_next_lut_index(struct ls_pcie_rc *pcie_rc)
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{
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if (pcie_rc->next_lut_index < PCIE_LUT_ENTRY_COUNT)
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return pcie_rc->next_lut_index++;
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else
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return -ENOSPC; /* LUT is full */
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}
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static void lut_writel(struct ls_pcie_rc *pcie_rc, unsigned int value,
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unsigned int offset)
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{
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struct ls_pcie *pcie = pcie_rc->pcie;
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if (pcie->big_endian)
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out_be32(pcie->lut + offset, value);
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else
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out_le32(pcie->lut + offset, value);
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}
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/*
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* Program a single LUT entry
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*/
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static void ls_pcie_lut_set_mapping(struct ls_pcie_rc *pcie_rc, int index,
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u32 devid, u32 streamid)
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{
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/* leave mask as all zeroes, want to match all bits */
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lut_writel(pcie_rc, devid << 16, PCIE_LUT_UDR(index));
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lut_writel(pcie_rc, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
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}
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/*
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* An msi-map is a property to be added to the pci controller
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* node. It is a table, where each entry consists of 4 fields
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* e.g.:
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*
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* msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
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* [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
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*/
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static void fdt_pcie_set_msi_map_entry_ls(void *blob,
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struct ls_pcie_rc *pcie_rc,
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u32 devid, u32 streamid)
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{
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u32 *prop;
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u32 phandle;
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int nodeoffset;
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uint svr;
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char *compat = NULL;
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struct ls_pcie *pcie = pcie_rc->pcie;
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/* find pci controller node */
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nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
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pcie_rc->dbi_res.start);
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if (nodeoffset < 0) {
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#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
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svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
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if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
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svr == SVR_LS2048A || svr == SVR_LS2044A ||
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svr == SVR_LS2081A || svr == SVR_LS2041A)
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compat = "fsl,ls2088a-pcie";
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else
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compat = CONFIG_FSL_PCIE_COMPAT;
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if (compat)
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nodeoffset = fdt_node_offset_by_compat_reg(blob,
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compat, pcie_rc->dbi_res.start);
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#endif
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if (nodeoffset < 0)
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return;
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}
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/* get phandle to MSI controller */
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prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
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if (prop == NULL) {
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debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
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__func__, pcie->idx);
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return;
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}
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phandle = fdt32_to_cpu(*prop);
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/* set one msi-map row */
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fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
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fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
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fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
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fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
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}
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/*
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* An iommu-map is a property to be added to the pci controller
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* node. It is a table, where each entry consists of 4 fields
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* e.g.:
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*
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* iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
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* [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
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*/
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static void fdt_pcie_set_iommu_map_entry_ls(void *blob,
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struct ls_pcie_rc *pcie_rc,
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u32 devid, u32 streamid)
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{
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u32 *prop;
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u32 iommu_map[4];
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int nodeoffset;
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int lenp;
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struct ls_pcie *pcie = pcie_rc->pcie;
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nodeoffset = fdt_pcie_get_nodeoffset(blob, pcie_rc);
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if (nodeoffset < 0)
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return;
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/* get phandle to iommu controller */
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prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
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if (prop == NULL) {
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debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
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__func__, pcie->idx);
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return;
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}
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/* set iommu-map row */
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iommu_map[0] = cpu_to_fdt32(devid);
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iommu_map[1] = *++prop;
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iommu_map[2] = cpu_to_fdt32(streamid);
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iommu_map[3] = cpu_to_fdt32(1);
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if (devid == 0) {
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fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
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iommu_map, 16);
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} else {
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fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
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}
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}
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static int fdt_fixup_pcie_device_ls(void *blob, pci_dev_t bdf,
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struct ls_pcie_rc *pcie_rc)
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{
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int streamid, index;
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streamid = pcie_next_streamid(pcie_rc->stream_id_cur,
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pcie_rc->pcie->idx);
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if (streamid < 0) {
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printf("ERROR: out of stream ids for BDF %d.%d.%d\n",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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return -ENOENT;
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}
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pcie_rc->stream_id_cur++;
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index = ls_pcie_next_lut_index(pcie_rc);
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if (index < 0) {
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printf("ERROR: out of LUT indexes for BDF %d.%d.%d\n",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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return -ENOENT;
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}
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/* map PCI b.d.f to streamID in LUT */
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ls_pcie_lut_set_mapping(pcie_rc, index, bdf >> 8, streamid);
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/* update msi-map in device tree */
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fdt_pcie_set_msi_map_entry_ls(blob, pcie_rc, bdf >> 8, streamid);
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/* update iommu-map in device tree */
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fdt_pcie_set_iommu_map_entry_ls(blob, pcie_rc, bdf >> 8, streamid);
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return 0;
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}
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struct extra_iommu_entry {
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int action;
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pci_dev_t bdf;
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int num_vfs;
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bool noari;
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};
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#define EXTRA_IOMMU_ENTRY_HOTPLUG 1
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#define EXTRA_IOMMU_ENTRY_VFS 2
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static struct extra_iommu_entry *get_extra_iommu_ents(void *blob,
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int nodeoffset,
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phys_addr_t addr,
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int *cnt)
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{
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const char *s, *p, *tok;
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struct extra_iommu_entry *entries;
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int i = 0, b, d, f;
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/*
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* Retrieve extra IOMMU configuration from env var or from device tree.
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* Env var is given priority.
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*/
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s = env_get("pci_iommu_extra");
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if (!s) {
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s = fdt_getprop(blob, nodeoffset, "pci-iommu-extra", NULL);
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} else {
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phys_addr_t pci_base;
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char *endp;
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/*
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* In env var case the config string has "pci@0x..." in
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* addition. Parse this part and match it by address against
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* the input pci controller's registers base address.
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*/
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tok = s;
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p = strchrnul(s + 1, ',');
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s = NULL;
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do {
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if (!strncmp(tok, "pci", 3)) {
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pci_base = simple_strtoul(tok + 4, &endp, 0);
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if (pci_base == addr) {
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s = endp + 1;
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break;
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}
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}
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p = strchrnul(p + 1, ',');
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tok = p + 1;
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} while (*p);
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}
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/*
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* If no env var or device tree property found or pci register base
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* address mismatches, bail out
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*/
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if (!s)
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return NULL;
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/*
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* In order to find how many action entries to allocate, count number
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* of actions by interating through the pairs of bdfs and actions.
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*/
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*cnt = 0;
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p = s;
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while (*p && strncmp(p, "pci", 3)) {
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if (*p == ',')
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(*cnt)++;
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p++;
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}
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if (!(*p))
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(*cnt)++;
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if (!(*cnt) || (*cnt) % 2) {
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printf("ERROR: invalid or odd extra iommu token count %d\n",
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*cnt);
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return NULL;
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}
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*cnt = (*cnt) / 2;
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entries = malloc((*cnt) * sizeof(*entries));
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if (!entries) {
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printf("ERROR: fail to allocate extra iommu entries\n");
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return NULL;
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}
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/*
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* Parse action entries one by one and store the information in the
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* newly allocated actions array.
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*/
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p = s;
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while (p) {
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/* Extract BDF */
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b = simple_strtoul(p, (char **)&p, 0); p++;
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d = simple_strtoul(p, (char **)&p, 0); p++;
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f = simple_strtoul(p, (char **)&p, 0); p++;
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entries[i].bdf = PCI_BDF(b, d, f);
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/* Parse action */
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if (!strncmp(p, "hp", 2)) {
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/* Hot-plug entry */
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entries[i].action = EXTRA_IOMMU_ENTRY_HOTPLUG;
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p += 2;
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} else if (!strncmp(p, "vfs", 3) ||
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!strncmp(p, "noari_vfs", 9)) {
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/* VFs or VFs with ARI disabled entry */
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entries[i].action = EXTRA_IOMMU_ENTRY_VFS;
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entries[i].noari = !strncmp(p, "noari_vfs", 9);
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/*
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* Parse and store total number of VFs to allocate
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* IOMMU entries for.
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*/
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p = strchr(p, '=');
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entries[i].num_vfs = simple_strtoul(p + 1, (char **)&p,
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0);
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if (*p)
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p++;
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} else {
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printf("ERROR: invalid action in extra iommu entry\n");
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free(entries);
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return NULL;
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}
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if (!(*p) || !strncmp(p, "pci", 3))
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break;
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i++;
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}
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return entries;
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}
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static void get_vf_offset_and_stride(struct udevice *dev, int sriov_pos,
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struct extra_iommu_entry *entry,
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u16 *offset, u16 *stride)
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{
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u16 tmp16;
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u32 tmp32;
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bool have_ari = false;
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int pos;
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struct udevice *pf_dev;
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dm_pci_read_config16(dev, sriov_pos + PCI_SRIOV_TOTAL_VF, &tmp16);
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if (entry->num_vfs > tmp16) {
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printf("WARN: requested no. of VFs %d exceeds total of %d\n",
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entry->num_vfs, tmp16);
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}
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/*
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* The code below implements the VF Discovery recomandations specified
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* in PCIe base spec "9.2.1.2 VF Discovery", quoted below:
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*
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* VF Discovery
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*
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* The First VF Offset and VF Stride fields in the SR-IOV extended
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* capability are 16-bit Routing ID offsets. These offsets are used to
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* compute the Routing IDs for the VFs with the following restrictions:
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* - The value in NumVFs in a PF (Section 9.3.3.7) may affect the
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* values in First VF Offset (Section 9.3.3.9) and VF Stride
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* (Section 9.3.3.10) of that PF.
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* - The value in ARI Capable Hierarchy (Section 9.3.3.3.5) in the
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* lowest-numbered PF of the Device (for example PF0) may affect
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* the values in First VF Offset and VF Stride in all PFs of the
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* Device.
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* - NumVFs of a PF may only be changed when VF Enable
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* (Section 9.3.3.3.1) of that PF is Clear.
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* - ARI Capable Hierarchy (Section 9.3.3.3.5) may only be changed
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* when VF Enable is Clear in all PFs of a Device.
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*/
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/* Clear VF enable for all PFs */
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device_foreach_child(pf_dev, dev->parent) {
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dm_pci_read_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL,
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&tmp16);
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tmp16 &= ~PCI_SRIOV_CTRL_VFE;
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dm_pci_write_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL,
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tmp16);
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}
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/* Obtain a reference to PF0 device */
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if (dm_pci_bus_find_bdf(PCI_BDF(PCI_BUS(entry->bdf),
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PCI_DEV(entry->bdf), 0), &pf_dev)) {
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printf("WARN: failed to get PF0\n");
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}
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if (entry->noari)
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goto skip_ari;
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/* Check that connected downstream port supports ARI Forwarding */
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pos = dm_pci_find_capability(dev->parent, PCI_CAP_ID_EXP);
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dm_pci_read_config32(dev->parent, pos + PCI_EXP_DEVCAP2, &tmp32);
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if (!(tmp32 & PCI_EXP_DEVCAP2_ARI))
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goto skip_ari;
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/* Check that PF supports Alternate Routing ID */
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if (!dm_pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI))
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goto skip_ari;
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/* Set ARI Capable Hierarcy for PF0 */
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dm_pci_read_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL, &tmp16);
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tmp16 |= PCI_SRIOV_CTRL_ARI;
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dm_pci_write_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL, tmp16);
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have_ari = true;
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skip_ari:
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if (!have_ari) {
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/*
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* No ARI support or disabled so clear ARI Capable Hierarcy
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* for PF0
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*/
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dm_pci_read_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL,
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&tmp16);
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tmp16 &= ~PCI_SRIOV_CTRL_ARI;
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dm_pci_write_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL,
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tmp16);
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}
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/* Set requested number of VFs */
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dm_pci_write_config16(dev, sriov_pos + PCI_SRIOV_NUM_VF,
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entry->num_vfs);
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/* Read VF stride and offset with the configs just made */
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dm_pci_read_config16(dev, sriov_pos + PCI_SRIOV_VF_OFFSET, offset);
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dm_pci_read_config16(dev, sriov_pos + PCI_SRIOV_VF_STRIDE, stride);
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if (have_ari) {
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/* Reset to default ARI Capable Hierarcy bit for PF0 */
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dm_pci_read_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL,
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&tmp16);
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tmp16 &= ~PCI_SRIOV_CTRL_ARI;
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dm_pci_write_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL,
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tmp16);
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}
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/* Reset to default the number of VFs */
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dm_pci_write_config16(dev, sriov_pos + PCI_SRIOV_NUM_VF, 0);
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}
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static int fdt_fixup_pci_vfs(void *blob, struct extra_iommu_entry *entry,
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struct ls_pcie_rc *pcie_rc)
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{
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struct udevice *dev, *bus;
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u16 vf_offset, vf_stride;
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int i, sriov_pos;
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pci_dev_t bdf;
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if (dm_pci_bus_find_bdf(entry->bdf, &dev)) {
|
|
printf("ERROR: BDF %d.%d.%d not found\n", PCI_BUS(entry->bdf),
|
|
PCI_DEV(entry->bdf), PCI_FUNC(entry->bdf));
|
|
return 0;
|
|
}
|
|
|
|
sriov_pos = dm_pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
|
|
if (!sriov_pos) {
|
|
printf("WARN: trying to set VFs on non-SRIOV dev\n");
|
|
return 0;
|
|
}
|
|
|
|
get_vf_offset_and_stride(dev, sriov_pos, entry, &vf_offset, &vf_stride);
|
|
|
|
for (bus = dev; device_is_on_pci_bus(bus);)
|
|
bus = bus->parent;
|
|
|
|
bdf = entry->bdf - PCI_BDF(dev_seq(bus), 0, 0) + (vf_offset << 8);
|
|
|
|
for (i = 0; i < entry->num_vfs; i++) {
|
|
if (fdt_fixup_pcie_device_ls(blob, bdf, pcie_rc) < 0)
|
|
return -1;
|
|
bdf += vf_stride << 8;
|
|
}
|
|
|
|
printf("Added %d iommu VF mappings for PF %d.%d.%d\n",
|
|
entry->num_vfs, PCI_BUS(entry->bdf),
|
|
PCI_DEV(entry->bdf), PCI_FUNC(entry->bdf));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void fdt_fixup_pcie_ls(void *blob)
|
|
{
|
|
struct udevice *dev, *bus;
|
|
struct ls_pcie_rc *pcie_rc;
|
|
pci_dev_t bdf;
|
|
struct extra_iommu_entry *entries;
|
|
int i, cnt, nodeoffset;
|
|
|
|
|
|
/* Scan all known buses */
|
|
for (pci_find_first_device(&dev);
|
|
dev;
|
|
pci_find_next_device(&dev)) {
|
|
for (bus = dev; device_is_on_pci_bus(bus);)
|
|
bus = bus->parent;
|
|
|
|
/* Only do the fixups for layerscape PCIe controllers */
|
|
if (!device_is_compatible(bus, "fsl,ls-pcie") &&
|
|
!device_is_compatible(bus, CONFIG_FSL_PCIE_COMPAT))
|
|
continue;
|
|
|
|
pcie_rc = dev_get_priv(bus);
|
|
|
|
/* the DT fixup must be relative to the hose first_busno */
|
|
bdf = dm_pci_get_bdf(dev) - PCI_BDF(dev_seq(bus), 0, 0);
|
|
|
|
if (fdt_fixup_pcie_device_ls(blob, bdf, pcie_rc) < 0)
|
|
break;
|
|
}
|
|
|
|
if (!IS_ENABLED(CONFIG_PCI_IOMMU_EXTRA_MAPPINGS))
|
|
goto skip;
|
|
|
|
list_for_each_entry(pcie_rc, &ls_pcie_list, list) {
|
|
nodeoffset = fdt_pcie_get_nodeoffset(blob, pcie_rc);
|
|
if (nodeoffset < 0) {
|
|
printf("ERROR: couldn't find pci node\n");
|
|
continue;
|
|
}
|
|
|
|
entries = get_extra_iommu_ents(blob, nodeoffset,
|
|
pcie_rc->dbi_res.start, &cnt);
|
|
if (!entries)
|
|
continue;
|
|
|
|
for (i = 0; i < cnt; i++) {
|
|
if (entries[i].action == EXTRA_IOMMU_ENTRY_HOTPLUG) {
|
|
bdf = entries[i].bdf;
|
|
printf("Added iommu map for hotplug %d.%d.%d\n",
|
|
PCI_BUS(bdf), PCI_DEV(bdf),
|
|
PCI_FUNC(bdf));
|
|
if (fdt_fixup_pcie_device_ls(blob, bdf,
|
|
pcie_rc) < 0) {
|
|
free(entries);
|
|
return;
|
|
}
|
|
} else if (entries[i].action == EXTRA_IOMMU_ENTRY_VFS) {
|
|
if (fdt_fixup_pci_vfs(blob, &entries[i],
|
|
pcie_rc) < 0) {
|
|
free(entries);
|
|
return;
|
|
}
|
|
} else {
|
|
printf("Invalid action %d for BDF %d.%d.%d\n",
|
|
entries[i].action,
|
|
PCI_BUS(entries[i].bdf),
|
|
PCI_DEV(entries[i].bdf),
|
|
PCI_FUNC(entries[i].bdf));
|
|
}
|
|
}
|
|
free(entries);
|
|
}
|
|
|
|
skip:
|
|
pcie_board_fix_fdt(blob);
|
|
}
|
|
#endif
|
|
|
|
static void ft_pcie_rc_fix(void *blob, struct ls_pcie_rc *pcie_rc)
|
|
{
|
|
int off;
|
|
struct ls_pcie *pcie = pcie_rc->pcie;
|
|
|
|
off = fdt_pcie_get_nodeoffset(blob, pcie_rc);
|
|
if (off < 0)
|
|
return;
|
|
|
|
if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
|
|
fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
|
|
else
|
|
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
|
|
}
|
|
|
|
static void ft_pcie_ep_fix(void *blob, struct ls_pcie_rc *pcie_rc)
|
|
{
|
|
int off;
|
|
struct ls_pcie *pcie = pcie_rc->pcie;
|
|
|
|
off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
|
|
pcie_rc->dbi_res.start);
|
|
if (off < 0)
|
|
return;
|
|
|
|
if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
|
|
fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
|
|
else
|
|
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
|
|
}
|
|
|
|
static void ft_pcie_ls_setup(void *blob, struct ls_pcie_rc *pcie_rc)
|
|
{
|
|
ft_pcie_ep_fix(blob, pcie_rc);
|
|
ft_pcie_rc_fix(blob, pcie_rc);
|
|
}
|
|
|
|
/* Fixup Kernel DT for PCIe */
|
|
void ft_pci_setup_ls(void *blob, struct bd_info *bd)
|
|
{
|
|
struct ls_pcie_rc *pcie_rc;
|
|
|
|
list_for_each_entry(pcie_rc, &ls_pcie_list, list)
|
|
ft_pcie_ls_setup(blob, pcie_rc);
|
|
|
|
#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
|
|
fdt_fixup_pcie_ls(blob);
|
|
#endif
|
|
}
|
|
|
|
#else /* !CONFIG_OF_BOARD_SETUP */
|
|
void ft_pci_setup_ls(void *blob, struct bd_info *bd)
|
|
{
|
|
}
|
|
#endif
|