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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-15 01:03:24 +09:00
cd0847fe63
The UniPhier EHCI driver (drivers/usb/host/ehci-uniphier.c) does
nothing special but set the base address and handle reset/clock.
Since commit 4feefdcfe9 ("usb: add clock support for generic EHCI"),
the generic one (drivers/usb/host/ehci-generic.c) can do those, too.
We no longer need to stick to the dedicated driver.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
59 lines
1.3 KiB
C
59 lines
1.3 KiB
C
/*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/io.h>
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#include "../init.h"
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#include "../sc-regs.h"
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void ph1_pro4_clk_init(void)
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{
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u32 tmp;
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/* deassert reset */
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tmp = readl(SC_RSTCTRL);
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#ifdef CONFIG_USB_XHCI_UNIPHIER
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tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 |
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SC_RSTCTRL_NRST_GIO;
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#endif
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#ifdef CONFIG_UNIPHIER_ETH
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tmp |= SC_RSTCTRL_NRST_ETHER;
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#endif
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#ifdef CONFIG_USB_EHCI
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tmp |= SC_RSTCTRL_NRST_STDMAC;
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#endif
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#ifdef CONFIG_NAND_DENALI
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tmp |= SC_RSTCTRL_NRST_NAND;
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#endif
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writel(tmp, SC_RSTCTRL);
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readl(SC_RSTCTRL); /* dummy read */
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#ifdef CONFIG_USB_XHCI_UNIPHIER
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tmp = readl(SC_RSTCTRL2);
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tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1;
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writel(tmp, SC_RSTCTRL2);
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readl(SC_RSTCTRL2); /* dummy read */
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#endif
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/* privide clocks */
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tmp = readl(SC_CLKCTRL);
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#ifdef CONFIG_USB_XHCI_UNIPHIER
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tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
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SC_CLKCTRL_CEN_GIO;
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#endif
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#ifdef CONFIG_UNIPHIER_ETH
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tmp |= SC_CLKCTRL_CEN_ETHER;
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#endif
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#ifdef CONFIG_USB_EHCI
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tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
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#endif
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#ifdef CONFIG_NAND_DENALI
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tmp |= SC_CLKCTRL_CEN_NAND;
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#endif
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writel(tmp, SC_CLKCTRL);
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readl(SC_CLKCTRL); /* dummy read */
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}
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