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https://github.com/brain-hackers/u-boot-brain
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![Timur Tabi](/assets/img/avatar_default.png)
Most 85xx boards can be built as a 32-bit or a 36-bit. Current code sometimes displays which of these is actually built, but it's inconsistent. This is especially problematic since the "default" build for a given 85xx board can be either one, so if you don't see a message, you can't always know which size is being used. Not only that, but each board includes code that displays the message, so there is duplication. The 'bdinfo' command has been updated to display this information, so we don't need to display it at boot time. The board-specific code is deleted. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
329 lines
7.5 KiB
C
329 lines
7.5 KiB
C
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <mmc.h>
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#include <netdev.h>
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#include <pci.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_ifc.h>
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#include <asm/fsl_pci.h>
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#ifndef CONFIG_SDCARD
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#include <hwconfig.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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#define GPIO4_PCIE_RESET_SET 0x08000000
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#define MUX_CPLD_CAN_UART 0x00
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#define MUX_CPLD_TDM 0x01
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#define MUX_CPLD_SPICS0_FLASH 0x00
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#define MUX_CPLD_SPICS0_SLIC 0x02
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#ifndef CONFIG_SDCARD
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struct cpld_data {
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u8 cpld_ver; /* cpld revision */
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u8 pcba_ver; /* pcb revision number */
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u8 twindie_ddr3;
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u8 res1[6];
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u8 bank_sel; /* NOR Flash bank */
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u8 res2[5];
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u8 usb2_sel;
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u8 res3[1];
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u8 porsw_sel;
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u8 tdm_can_sel;
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u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
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u8 por0; /* POR Options */
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u8 por1; /* POR Options */
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u8 por2; /* POR Options */
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u8 por3; /* POR Options */
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};
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void cpld_show(void)
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{
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struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
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printf("CPLD: V%x.%x PCBA: V%x.0\n",
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in_8(&cpld_data->cpld_ver) & 0xF0,
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in_8(&cpld_data->cpld_ver) & 0x0F,
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in_8(&cpld_data->pcba_ver) & 0x0F);
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#ifdef CONFIG_DEBUG
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printf("twindie_ddr =%x\n",
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in_8(&cpld_data->twindie_ddr3));
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printf("bank_sel =%x\n",
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in_8(&cpld_data->bank_sel));
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printf("usb2_sel =%x\n",
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in_8(&cpld_data->usb2_sel));
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printf("porsw_sel =%x\n",
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in_8(&cpld_data->porsw_sel));
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printf("tdm_can_sel =%x\n",
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in_8(&cpld_data->tdm_can_sel));
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printf("tdm_can_sel =%x\n",
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in_8(&cpld_data->tdm_can_sel));
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printf("spi_cs0_sel =%x\n",
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in_8(&cpld_data->spi_cs0_sel));
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printf("bcsr0 =%x\n",
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in_8(&cpld_data->bcsr0));
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printf("bcsr1 =%x\n",
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in_8(&cpld_data->bcsr1));
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printf("bcsr2 =%x\n",
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in_8(&cpld_data->bcsr2));
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printf("bcsr3 =%x\n",
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in_8(&cpld_data->bcsr3));
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#endif
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}
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#endif
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int board_early_init_f(void)
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{
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ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
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#ifndef CONFIG_SDCARD
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struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
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/* Clock configuration to access CPLD using IFC(GPCM) */
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setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
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#endif
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/*
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* Reset PCIe slots via GPIO4
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*/
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setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
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setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
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return 0;
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}
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int board_early_init_r(void)
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{
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#ifndef CONFIG_SDCARD
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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/* invalidate existing TLB entry for flash */
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disable_tlb(flash_esel);
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_16M, 1);
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set_tlb(1, flashbase + 0x1000000,
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CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
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#endif
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return 0;
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}
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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fsl_pcie_init_board(0);
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}
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#endif /* ifdef CONFIG_PCI */
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int checkboard(void)
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{
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struct cpu_type *cpu;
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cpu = gd->cpu;
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printf("Board: %sRDB\n", cpu->name);
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return 0;
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}
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#ifdef CONFIG_TSEC_ENET
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int board_eth_init(bd_t *bis)
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{
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struct fsl_pq_mdio_info mdio_info;
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struct tsec_info_struct tsec_info[4];
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struct cpu_type *cpu;
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int num = 0;
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cpu = gd->cpu;
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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num++;
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#endif
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#ifdef CONFIG_TSEC3
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/* P1014 and it's derivatives do not support eTSEC3 */
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if (cpu->soc_ver != SVR_P1014 && cpu->soc_ver != SVR_P1014_E) {
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SET_STD_TSEC_INFO(tsec_info[num], 3);
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num++;
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}
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#endif
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if (!num) {
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printf("No TSECs initialized\n");
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return 0;
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}
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mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
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mdio_info.name = DEFAULT_MII_NAME;
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fsl_pq_mdio_init(bis, &mdio_info);
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tsec_eth_init(bis, tsec_info, num);
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return pci_eth_init(bis);
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}
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#endif
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#if defined(CONFIG_OF_BOARD_SETUP)
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void fdt_del_flexcan(void *blob)
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{
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int nodeoff = 0;
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while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
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"fsl,flexcan-v1.0")) >= 0) {
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fdt_del_node(blob, nodeoff);
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}
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}
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void fdt_del_spi_flash(void *blob)
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{
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int nodeoff = 0;
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while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
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"spansion,s25sl12801")) >= 0) {
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fdt_del_node(blob, nodeoff);
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}
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}
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void fdt_del_spi_slic(void *blob)
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{
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int nodeoff = 0;
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while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
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"zarlink,le88266")) >= 0) {
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fdt_del_node(blob, nodeoff);
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}
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}
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void fdt_del_tdm(void *blob)
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{
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int nodeoff = 0;
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while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
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"fsl,starlite-tdm")) >= 0) {
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fdt_del_node(blob, nodeoff);
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}
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}
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void ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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struct cpu_type *cpu;
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cpu = gd->cpu;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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#if defined(CONFIG_PCI)
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FT_FSL_PCI_SETUP;
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#endif
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#if defined(CONFIG_HAS_FSL_DR_USB)
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fdt_fixup_dr_usb(blob, bd);
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#endif
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/* P1014 and it's derivatives don't support CAN and eTSEC3 */
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if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) {
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fdt_del_flexcan(blob);
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fdt_del_node_and_alias(blob, "ethernet2");
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}
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#ifndef CONFIG_SDCARD
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if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
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printf("fdt CAN");
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fdt_del_tdm(blob);
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fdt_del_spi_slic(blob);
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}
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#ifndef CONFIG_SPIFLASH
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else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
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printf("fdt TDM");
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fdt_del_flexcan(blob);
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fdt_del_spi_flash(blob);
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}
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#endif
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#endif
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}
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#endif
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#ifndef CONFIG_SDCARD
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int misc_init_r(void)
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{
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struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
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clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
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MPC85xx_PMUXCR_CAN1_UART |
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MPC85xx_PMUXCR_CAN2_TDM |
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MPC85xx_PMUXCR_CAN2_UART);
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out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
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}
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#ifndef CONFIG_SPIFLASH
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if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
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printf("TDM");
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clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
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MPC85xx_PMUXCR_CAN1_UART);
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setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
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MPC85xx_PMUXCR_CAN1_TDM);
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clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
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setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
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out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
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out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
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}
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#endif
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return 0;
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}
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#endif
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