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https://github.com/brain-hackers/u-boot-brain
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fbfd92bf9b
U-Boot SPL can be run in a different privilege mode from U-Boot proper. Add new configuration entries for SPL to allow the run mode to be configured independently of U-Boot proper. Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE configuration symbols to also cover the SPL equivalents. Ensure that files compatible with only one privilege mode are not included in builds targeting an incompatible privilege mode. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
22 lines
563 B
Plaintext
22 lines
563 B
Plaintext
config RISCV_NDS
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bool
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select ARCH_EARLY_INIT_R
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imply CPU
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imply CPU_RISCV
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imply RISCV_TIMER
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imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
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imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
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help
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Run U-Boot on AndeStar V5 platforms and use some specific features
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which are provided by Andes Technology AndeStar V5 families.
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if RISCV_NDS
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config RISCV_NDS_CACHE
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bool "AndeStar V5 families specific cache support"
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depends on RISCV_MMODE || SPL_RISCV_MMODE
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help
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Provide Andes Technology AndeStar V5 families specific cache support.
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endif
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