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![Haikun Wang](/assets/img/avatar_default.png)
DSPI has pin muxing with SDHC and other IPs, this patch check the value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check the "hwconfig" variable. If those pins are configured to DSPI and "hwconfig" enable DSPI, set the BRDCFG5 of QIXIS FPGA to configure the routing to on-board SPI memory. Otherwise will configure to SDHC. DSPI is enabled in "hwconfig" by appending "dspi", eg. setenv hwconfig "$hwconfig;dspi" Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
330 lines
6.6 KiB
C
330 lines
6.6 KiB
C
/*
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* Copyright 2015 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <errno.h>
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#include <netdev.h>
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#include <fsl_ifc.h>
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#include <fsl_ddr.h>
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#include <asm/io.h>
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#include <fdt_support.h>
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#include <libfdt.h>
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#include <fsl_debug_server.h>
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#include <fsl-mc/fsl_mc.h>
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#include <environment.h>
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#include <i2c.h>
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#include <asm/arch-fsl-lsch3/soc.h>
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#include <hwconfig.h>
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#include "../common/qixis.h"
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#include "ls2085aqds_qixis.h"
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#define PIN_MUX_SEL_SDHC 0x00
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#define PIN_MUX_SEL_DSPI 0x0a
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#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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MUX_TYPE_SDHC,
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MUX_TYPE_DSPI,
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};
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unsigned long long get_qixis_addr(void)
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{
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unsigned long long addr;
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if (gd->flags & GD_FLG_RELOC)
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addr = QIXIS_BASE_PHYS;
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else
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addr = QIXIS_BASE_PHYS_EARLY;
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/*
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* IFC address under 256MB is mapped to 0x30000000, any address above
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* is mapped to 0x5_10000000 up to 4GB.
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*/
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addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
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return addr;
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}
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int checkboard(void)
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{
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char buf[64];
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u8 sw;
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static const char *const freq[] = {"100", "125", "156.25",
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"100 separate SSCG"};
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int clock;
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cpu_name(buf);
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printf("Board: %s-QDS, ", buf);
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sw = QIXIS_READ(arch);
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printf("Board Arch: V%d, ", sw >> 4);
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printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
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memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
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if (sw < 0x8)
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printf("vBank: %d\n", sw);
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else if (sw == 0x8)
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puts("PromJet\n");
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else if (sw == 0x9)
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puts("NAND\n");
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else if (sw == 0x15)
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printf("IFCCard\n");
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else
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printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
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printf("FPGA: v%d (%s), build %d",
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(int)QIXIS_READ(scver), qixis_read_tag(buf),
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(int)qixis_read_minor());
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/* the timestamp string contains "\n" at the end */
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printf(" on %s", qixis_read_time(buf));
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/*
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* Display the actual SERDES reference clocks as configured by the
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* dip switches on the board. Note that the SWx registers could
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* technically be set to force the reference clocks to match the
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* values that the SERDES expects (or vice versa). For now, however,
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* we just display both values and hope the user notices when they
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* don't match.
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*/
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puts("SERDES1 Reference : ");
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sw = QIXIS_READ(brdcfg[2]);
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clock = (sw >> 6) & 3;
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printf("Clock1 = %sMHz ", freq[clock]);
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clock = (sw >> 4) & 3;
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printf("Clock2 = %sMHz", freq[clock]);
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puts("\nSERDES2 Reference : ");
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clock = (sw >> 2) & 3;
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printf("Clock1 = %sMHz ", freq[clock]);
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clock = (sw >> 0) & 3;
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printf("Clock2 = %sMHz\n", freq[clock]);
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return 0;
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}
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unsigned long get_board_sys_clk(void)
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{
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u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
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switch (sysclk_conf & 0x0F) {
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case QIXIS_SYSCLK_83:
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return 83333333;
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case QIXIS_SYSCLK_100:
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return 100000000;
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case QIXIS_SYSCLK_125:
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return 125000000;
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case QIXIS_SYSCLK_133:
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return 133333333;
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case QIXIS_SYSCLK_150:
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return 150000000;
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case QIXIS_SYSCLK_160:
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return 160000000;
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case QIXIS_SYSCLK_166:
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return 166666666;
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}
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return 66666666;
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}
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unsigned long get_board_ddr_clk(void)
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{
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u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
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switch ((ddrclk_conf & 0x30) >> 4) {
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case QIXIS_DDRCLK_100:
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return 100000000;
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case QIXIS_DDRCLK_125:
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return 125000000;
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case QIXIS_DDRCLK_133:
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return 133333333;
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}
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return 66666666;
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}
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int select_i2c_ch_pca9547(u8 ch)
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{
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int ret;
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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}
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return 0;
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}
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int config_board_mux(int ctrl_type)
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{
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u8 reg5;
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reg5 = QIXIS_READ(brdcfg[5]);
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switch (ctrl_type) {
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case MUX_TYPE_SDHC:
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reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
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break;
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case MUX_TYPE_DSPI:
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reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
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break;
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default:
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printf("Wrong mux interface type\n");
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return -1;
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}
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QIXIS_WRITE(brdcfg[5], reg5);
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return 0;
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}
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int board_init(void)
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{
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char *env_hwconfig;
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u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
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u32 val;
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init_final_memctl_regs();
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val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
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env_hwconfig = getenv("hwconfig");
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if (hwconfig_f("dspi", env_hwconfig) &&
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DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
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config_board_mux(MUX_TYPE_DSPI);
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else
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config_board_mux(MUX_TYPE_SDHC);
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#ifdef CONFIG_ENV_IS_NOWHERE
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gd->env_addr = (ulong)&default_environment[0];
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#endif
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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return 0;
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}
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int board_early_init_f(void)
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{
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fsl_lsch3_early_init_f();
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return 0;
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}
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void detail_board_ddr_info(void)
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{
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puts("\nDDR ");
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print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
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print_ddr_info(0);
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if (gd->bd->bi_dram[2].size) {
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puts("\nDP-DDR ");
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print_size(gd->bd->bi_dram[2].size, "");
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print_ddr_info(CONFIG_DP_DDR_CTRL);
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}
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}
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int dram_init(void)
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{
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gd->ram_size = initdram(0);
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return 0;
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}
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#if defined(CONFIG_ARCH_MISC_INIT)
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int arch_misc_init(void)
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{
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#ifdef CONFIG_FSL_DEBUG_SERVER
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debug_server_init();
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#endif
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return 0;
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}
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#endif
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unsigned long get_dram_size_to_hide(void)
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{
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unsigned long dram_to_hide = 0;
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/* Carve the Debug Server private DRAM block from the end of DRAM */
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#ifdef CONFIG_FSL_DEBUG_SERVER
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dram_to_hide += debug_server_get_dram_block_size();
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#endif
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/* Carve the MC private DRAM block from the end of DRAM */
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#ifdef CONFIG_FSL_MC_ENET
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dram_to_hide += mc_get_dram_block_size();
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#endif
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return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
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}
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#ifdef CONFIG_FSL_MC_ENET
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void fdt_fixup_board_enet(void *fdt)
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{
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int offset;
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offset = fdt_path_offset(fdt, "/fsl-mc");
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if (offset < 0)
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offset = fdt_path_offset(fdt, "/fsl,dprc@0");
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if (offset < 0) {
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printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
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__func__, offset);
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return;
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}
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if (get_mc_boot_status() == 0)
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fdt_status_okay(fdt, offset);
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else
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fdt_status_fail(fdt, offset);
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}
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#endif
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#ifdef CONFIG_OF_BOARD_SETUP
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int ft_board_setup(void *blob, bd_t *bd)
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{
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u64 base[CONFIG_NR_DRAM_BANKS];
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u64 size[CONFIG_NR_DRAM_BANKS];
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ft_cpu_setup(blob, bd);
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/* fixup DT for the two GPP DDR banks */
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base[0] = gd->bd->bi_dram[0].start;
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size[0] = gd->bd->bi_dram[0].size;
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base[1] = gd->bd->bi_dram[1].start;
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size[1] = gd->bd->bi_dram[1].size;
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fdt_fixup_memory_banks(blob, base, size, 2);
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#ifdef CONFIG_FSL_MC_ENET
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fdt_fixup_board_enet(blob);
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fsl_mc_ldpaa_exit(bd);
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#endif
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return 0;
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}
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#endif
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void qixis_dump_switch(void)
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{
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int i, nr_of_cfgsw;
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QIXIS_WRITE(cms[0], 0x00);
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nr_of_cfgsw = QIXIS_READ(cms[1]);
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puts("DIP switch settings dump:\n");
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for (i = 1; i <= nr_of_cfgsw; i++) {
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QIXIS_WRITE(cms[0], i);
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printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
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}
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}
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