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Ludwig Zenz 0481bef035 ARM: imx6: DHCOM i.MX6 PDK: ddr init for 32bit bus and 4GBit chips 
Support 1GIB + 2GIB DDR3 with 64bit bus width and 512MIB + 1GIB with 32bit bus width

Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
2018-07-23 11:02:14 +02:00
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dh_imx6 ARM: imx6: DHCOM i.MX6 PDK: ddr init for 32bit bus and 4GBit chips 2018-07-23 11:02:14 +02:00