mirror of
https://github.com/brain-hackers/u-boot-brain
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a13cbf5f20
UART booting is supported on this SoC, but via UART3 rather than UART1. Because of this we must change the board to use UART3 for all console access (only one UART is exposed on this board and a slight HW mod is required to switch UARTs). Signed-off-by: Minal Shah <minal.shah@ti.com> [trini: Make apply to mainline, reword commit] Signed-off-by: Tom Rini <trini@ti.com>
76 lines
2.1 KiB
C
76 lines
2.1 KiB
C
/*
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* (C) Copyright 2013
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* Texas Instruments Incorporated.
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* Lokesh Vutla <lokeshvutla@ti.com>
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*
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* Configuration settings for the TI DRA7XX board.
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* See omap5_common.h for omap5 common settings.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_DRA7XX_EVM_H
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#define __CONFIG_DRA7XX_EVM_H
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#define CONFIG_DRA7XX
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/* MMC ENV related defines */
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
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#define CONFIG_ENV_OFFSET 0xE0000
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
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#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
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#define CONFIG_CMD_SAVEENV
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#if (CONFIG_CONS_INDEX == 1)
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#define CONSOLEDEV "ttyO0"
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#elif (CONFIG_CONS_INDEX == 3)
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#define CONSOLEDEV "ttyO2"
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#endif
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#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
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#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
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#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_OMAP_ABE_SYSCK
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#include <configs/omap5_common.h>
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/* CPSW Ethernet */
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#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
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#define CONFIG_CMD_DHCP
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#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_NET_RETRY_COUNT 10
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_MII
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#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
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#define CONFIG_MII /* Required in net/eth.c */
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#define CONFIG_PHY_GIGE /* per-board part of CPSW */
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_ADDR 2
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/* SPI */
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#undef CONFIG_OMAP3_SPI
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#define CONFIG_TI_QSPI
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_SPANSION
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#define CONFIG_CMD_SF
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#define CONFIG_CMD_SPI
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#define CONFIG_TI_SPI_MMAP
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#define CONFIG_SF_DEFAULT_SPEED 48000000
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#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
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/* SPI SPL */
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_BUS 0
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#define CONFIG_SPL_SPI_CS 0
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
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#endif /* __CONFIG_DRA7XX_EVM_H */
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