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![Wolfgang Denk](/assets/img/avatar_default.png)
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
62 lines
1.8 KiB
C
62 lines
1.8 KiB
C
/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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* Aneesh V <aneesh@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef ARMV7_H
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#define ARMV7_H
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#include <linux/types.h>
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/* Cortex-A9 revisions */
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#define MIDR_CORTEX_A9_R0P1 0x410FC091
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#define MIDR_CORTEX_A9_R1P2 0x411FC092
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#define MIDR_CORTEX_A9_R1P3 0x411FC093
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#define MIDR_CORTEX_A9_R2P10 0x412FC09A
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/* Cortex-A15 revisions */
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#define MIDR_CORTEX_A15_R0P0 0x410FC0F0
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#define MIDR_CORTEX_A15_R2P2 0x412FC0F2
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/* CCSIDR */
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#define CCSIDR_LINE_SIZE_OFFSET 0
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#define CCSIDR_LINE_SIZE_MASK 0x7
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#define CCSIDR_ASSOCIATIVITY_OFFSET 3
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#define CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3)
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#define CCSIDR_NUM_SETS_OFFSET 13
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#define CCSIDR_NUM_SETS_MASK (0x7FFF << 13)
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/*
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* Values for InD field in CSSELR
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* Selects the type of cache
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*/
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#define ARMV7_CSSELR_IND_DATA_UNIFIED 0
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#define ARMV7_CSSELR_IND_INSTRUCTION 1
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/* Values for Ctype fields in CLIDR */
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#define ARMV7_CLIDR_CTYPE_NO_CACHE 0
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#define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1
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#define ARMV7_CLIDR_CTYPE_DATA_ONLY 2
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#define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3
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#define ARMV7_CLIDR_CTYPE_UNIFIED 4
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/*
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* CP15 Barrier instructions
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* Please note that we have separate barrier instructions in ARMv7
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* However, we use the CP15 based instructtions because we use
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* -march=armv5 in U-Boot
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*/
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#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0))
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#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
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#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
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void v7_outer_cache_enable(void);
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void v7_outer_cache_disable(void);
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void v7_outer_cache_flush_all(void);
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void v7_outer_cache_inval_all(void);
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void v7_outer_cache_flush_range(u32 start, u32 end);
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void v7_outer_cache_inval_range(u32 start, u32 end);
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#endif
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