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![Patrice Chotard](/assets/img/avatar_default.png)
If CONFIG_CLK flag is not set, compilation raises the following error message: drivers/ram/stm32_sdram.c: In function 'stm32_fmc_probe': drivers/ram/stm32_sdram.c:154:2: error: 'ret' undeclared (first use in this function) ret = stm32_sdram_init(dev); Signed-off-by: Patrice Chotard <patrice.chotard@st.com> cc: Vikas Manocha <vikas.manocha@st.com>
180 lines
4.3 KiB
C
180 lines
4.3 KiB
C
/*
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* (C) Copyright 2017
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* Vikas Manocha, <vikas.manocha@st.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <ram.h>
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#include <asm/io.h>
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#include <asm/arch/fmc.h>
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#include <asm/arch/stm32.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct stm32_sdram_control {
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u8 no_columns;
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u8 no_rows;
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u8 memory_width;
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u8 no_banks;
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u8 cas_latency;
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u8 sdclk;
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u8 rd_burst;
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u8 rd_pipe_delay;
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};
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struct stm32_sdram_timing {
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u8 tmrd;
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u8 txsr;
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u8 tras;
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u8 trc;
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u8 trp;
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u8 twr;
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u8 trcd;
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};
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struct stm32_sdram_params {
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u8 no_sdram_banks;
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struct stm32_sdram_control sdram_control;
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struct stm32_sdram_timing sdram_timing;
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u32 sdram_ref_count;
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};
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#define SDRAM_MODE_BL_SHIFT 0
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#define SDRAM_MODE_CAS_SHIFT 4
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#define SDRAM_MODE_BL 0
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int stm32_sdram_init(struct udevice *dev)
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{
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struct stm32_sdram_params *params = dev_get_platdata(dev);
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writel(params->sdram_control.sdclk << FMC_SDCR_SDCLK_SHIFT
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| params->sdram_control.cas_latency << FMC_SDCR_CAS_SHIFT
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| params->sdram_control.no_banks << FMC_SDCR_NB_SHIFT
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| params->sdram_control.memory_width << FMC_SDCR_MWID_SHIFT
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| params->sdram_control.no_rows << FMC_SDCR_NR_SHIFT
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| params->sdram_control.no_columns << FMC_SDCR_NC_SHIFT
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| params->sdram_control.rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
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| params->sdram_control.rd_burst << FMC_SDCR_RBURST_SHIFT,
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&STM32_SDRAM_FMC->sdcr1);
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writel(params->sdram_timing.trcd << FMC_SDTR_TRCD_SHIFT
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| params->sdram_timing.trp << FMC_SDTR_TRP_SHIFT
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| params->sdram_timing.twr << FMC_SDTR_TWR_SHIFT
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| params->sdram_timing.trc << FMC_SDTR_TRC_SHIFT
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| params->sdram_timing.tras << FMC_SDTR_TRAS_SHIFT
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| params->sdram_timing.txsr << FMC_SDTR_TXSR_SHIFT
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| params->sdram_timing.tmrd << FMC_SDTR_TMRD_SHIFT,
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&STM32_SDRAM_FMC->sdtr1);
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writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK,
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&STM32_SDRAM_FMC->sdcmr);
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udelay(200); /* 200 us delay, page 10, "Power-Up" */
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FMC_BUSY_WAIT();
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writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE,
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&STM32_SDRAM_FMC->sdcmr);
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udelay(100);
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FMC_BUSY_WAIT();
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writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH
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| 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
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udelay(100);
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FMC_BUSY_WAIT();
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writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
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| params->sdram_control.cas_latency << SDRAM_MODE_CAS_SHIFT)
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<< FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
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&STM32_SDRAM_FMC->sdcmr);
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udelay(100);
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FMC_BUSY_WAIT();
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writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL,
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&STM32_SDRAM_FMC->sdcmr);
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FMC_BUSY_WAIT();
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/* Refresh timer */
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writel((params->sdram_ref_count) << 1, &STM32_SDRAM_FMC->sdrtr);
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return 0;
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}
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static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
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{
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int ret;
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int node = dev_of_offset(dev);
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const void *blob = gd->fdt_blob;
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struct stm32_sdram_params *params = dev_get_platdata(dev);
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params->no_sdram_banks = fdtdec_get_uint(blob, node, "mr-nbanks", 1);
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debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
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fdt_for_each_subnode(node, blob, node) {
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ret = fdtdec_get_byte_array(blob, node, "st,sdram-control",
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(u8 *)¶ms->sdram_control,
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sizeof(params->sdram_control));
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if (ret)
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return ret;
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ret = fdtdec_get_byte_array(blob, node, "st,sdram-timing",
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(u8 *)¶ms->sdram_timing,
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sizeof(params->sdram_timing));
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if (ret)
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return ret;
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params->sdram_ref_count = fdtdec_get_int(blob, node,
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"st,sdram-refcount", 8196);
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}
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return 0;
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}
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static int stm32_fmc_probe(struct udevice *dev)
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{
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int ret;
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#ifdef CONFIG_CLK
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struct clk clk;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&clk);
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if (ret) {
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dev_err(dev, "failed to enable clock\n");
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return ret;
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}
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#endif
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ret = stm32_sdram_init(dev);
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if (ret)
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return ret;
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return 0;
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}
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static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info)
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{
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return 0;
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}
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static struct ram_ops stm32_fmc_ops = {
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.get_info = stm32_fmc_get_info,
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};
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static const struct udevice_id stm32_fmc_ids[] = {
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{ .compatible = "st,stm32-fmc" },
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{ }
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};
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U_BOOT_DRIVER(stm32_fmc) = {
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.name = "stm32_fmc",
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.id = UCLASS_RAM,
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.of_match = stm32_fmc_ids,
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.ops = &stm32_fmc_ops,
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.ofdata_to_platdata = stm32_fmc_ofdata_to_platdata,
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.probe = stm32_fmc_probe,
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.platdata_auto_alloc_size = sizeof(struct stm32_sdram_params),
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};
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