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https://github.com/brain-hackers/u-boot-brain
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![Lukasz Majewski](/assets/img/avatar_default.png)
Up till this commit passing NULL as input parameter was allowed, but not handled properly. When one passed NULL to one of this function parameters, the code was executed causing data abort. However, what is more interesting, the abort was not caught because of code execution in HYP mode with masked CPSR A bit ("Imprecise Data Abort mask bit). The TI's AM57xx SoC switch to HYP mode with A bit masked in lowlevel_init.S due to SMC call. Such operation (by default) is performed in SoC ROM code. The problem would pop up when one: - Switch back to SVC mode after disabling LPAE support - Somebody enables A bit (by executing cpsie a asm instruction) and then the previously described exception would be caught. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
923 lines
25 KiB
C
923 lines
25 KiB
C
/*
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*
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* Clock initialization for OMAP4
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Aneesh V <aneesh@ti.com>
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*
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* Based on previous work by:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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* Rajendra Nayak <rnayak@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/omap_common.h>
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#include <asm/gpio.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/utils.h>
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#include <asm/omap_gpio.h>
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#include <asm/emif.h>
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#ifndef CONFIG_SPL_BUILD
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/*
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* printing to console doesn't work unless
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* this code is executed from SPL
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*/
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#define printf(fmt, args...)
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#define puts(s)
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#endif
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const u32 sys_clk_array[8] = {
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12000000, /* 12 MHz */
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20000000, /* 20 MHz */
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16800000, /* 16.8 MHz */
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19200000, /* 19.2 MHz */
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26000000, /* 26 MHz */
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27000000, /* 27 MHz */
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38400000, /* 38.4 MHz */
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};
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static inline u32 __get_sys_clk_index(void)
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{
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s8 ind;
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/*
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* For ES1 the ROM code calibration of sys clock is not reliable
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* due to hw issue. So, use hard-coded value. If this value is not
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* correct for any board over-ride this function in board file
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* From ES2.0 onwards you will get this information from
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* CM_SYS_CLKSEL
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*/
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if (omap_revision() == OMAP4430_ES1_0)
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ind = OMAP_SYS_CLK_IND_38_4_MHZ;
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else {
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/* SYS_CLKSEL - 1 to match the dpll param array indices */
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ind = (readl((*prcm)->cm_sys_clksel) &
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CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
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}
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return ind;
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}
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u32 get_sys_clk_index(void)
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__attribute__ ((weak, alias("__get_sys_clk_index")));
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u32 get_sys_clk_freq(void)
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{
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u8 index = get_sys_clk_index();
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return sys_clk_array[index];
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}
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void setup_post_dividers(u32 const base, const struct dpll_params *params)
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{
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
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/* Setup post-dividers */
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if (params->m2 >= 0)
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writel(params->m2, &dpll_regs->cm_div_m2_dpll);
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if (params->m3 >= 0)
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writel(params->m3, &dpll_regs->cm_div_m3_dpll);
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if (params->m4_h11 >= 0)
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writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
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if (params->m5_h12 >= 0)
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writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
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if (params->m6_h13 >= 0)
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writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
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if (params->m7_h14 >= 0)
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writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
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if (params->h21 >= 0)
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writel(params->h21, &dpll_regs->cm_div_h21_dpll);
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if (params->h22 >= 0)
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writel(params->h22, &dpll_regs->cm_div_h22_dpll);
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if (params->h23 >= 0)
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writel(params->h23, &dpll_regs->cm_div_h23_dpll);
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if (params->h24 >= 0)
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writel(params->h24, &dpll_regs->cm_div_h24_dpll);
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}
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static inline void do_bypass_dpll(u32 const base)
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{
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struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
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clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
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CM_CLKMODE_DPLL_DPLL_EN_MASK,
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DPLL_EN_FAST_RELOCK_BYPASS <<
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CM_CLKMODE_DPLL_EN_SHIFT);
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}
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static inline void wait_for_bypass(u32 const base)
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{
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
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if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
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LDELAY)) {
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printf("Bypassing DPLL failed %x\n", base);
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}
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}
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static inline void do_lock_dpll(u32 const base)
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{
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
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clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
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CM_CLKMODE_DPLL_DPLL_EN_MASK,
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DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
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}
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static inline void wait_for_lock(u32 const base)
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{
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
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if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
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&dpll_regs->cm_idlest_dpll, LDELAY)) {
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printf("DPLL locking failed for %x\n", base);
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hang();
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}
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}
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inline u32 check_for_lock(u32 const base)
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{
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
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u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
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return lock;
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}
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const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
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{
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u32 sysclk_ind = get_sys_clk_index();
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return &dpll_data->mpu[sysclk_ind];
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}
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const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
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{
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u32 sysclk_ind = get_sys_clk_index();
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return &dpll_data->core[sysclk_ind];
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}
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const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
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{
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u32 sysclk_ind = get_sys_clk_index();
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return &dpll_data->per[sysclk_ind];
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}
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const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
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{
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u32 sysclk_ind = get_sys_clk_index();
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return &dpll_data->iva[sysclk_ind];
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}
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const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
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{
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u32 sysclk_ind = get_sys_clk_index();
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return &dpll_data->usb[sysclk_ind];
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}
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const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
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{
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#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
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u32 sysclk_ind = get_sys_clk_index();
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return &dpll_data->abe[sysclk_ind];
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#else
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return dpll_data->abe;
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#endif
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}
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static const struct dpll_params *get_ddr_dpll_params
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(struct dplls const *dpll_data)
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{
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u32 sysclk_ind = get_sys_clk_index();
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if (!dpll_data->ddr)
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return NULL;
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return &dpll_data->ddr[sysclk_ind];
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}
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#ifdef CONFIG_DRIVER_TI_CPSW
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static const struct dpll_params *get_gmac_dpll_params
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(struct dplls const *dpll_data)
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{
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u32 sysclk_ind = get_sys_clk_index();
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if (!dpll_data->gmac)
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return NULL;
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return &dpll_data->gmac[sysclk_ind];
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}
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#endif
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static void do_setup_dpll(u32 const base, const struct dpll_params *params,
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u8 lock, char *dpll)
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{
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u32 temp, M, N;
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
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if (!params)
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return;
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temp = readl(&dpll_regs->cm_clksel_dpll);
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if (check_for_lock(base)) {
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/*
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* The Dpll has already been locked by rom code using CH.
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* Check if M,N are matching with Ideal nominal opp values.
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* If matches, skip the rest otherwise relock.
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*/
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M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
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N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
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if ((M != (params->m)) || (N != (params->n))) {
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debug("\n %s Dpll locked, but not for ideal M = %d,"
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"N = %d values, current values are M = %d,"
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"N= %d" , dpll, params->m, params->n,
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M, N);
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} else {
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/* Dpll locked with ideal values for nominal opps. */
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debug("\n %s Dpll already locked with ideal"
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"nominal opp values", dpll);
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bypass_dpll(base);
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goto setup_post_dividers;
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}
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}
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bypass_dpll(base);
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/* Set M & N */
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temp &= ~CM_CLKSEL_DPLL_M_MASK;
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temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
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temp &= ~CM_CLKSEL_DPLL_N_MASK;
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temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
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writel(temp, &dpll_regs->cm_clksel_dpll);
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setup_post_dividers:
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setup_post_dividers(base, params);
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/* Lock */
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if (lock)
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do_lock_dpll(base);
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/* Wait till the DPLL locks */
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if (lock)
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wait_for_lock(base);
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}
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u32 omap_ddr_clk(void)
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{
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u32 ddr_clk, sys_clk_khz, omap_rev, divider;
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const struct dpll_params *core_dpll_params;
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omap_rev = omap_revision();
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sys_clk_khz = get_sys_clk_freq() / 1000;
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core_dpll_params = get_core_dpll_params(*dplls_data);
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debug("sys_clk %d\n ", sys_clk_khz * 1000);
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/* Find Core DPLL locked frequency first */
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ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
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(core_dpll_params->n + 1);
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if (omap_rev < OMAP5430_ES1_0) {
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/*
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* DDR frequency is PHY_ROOT_CLK/2
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* PHY_ROOT_CLK = Fdpll/2/M2
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*/
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divider = 4;
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} else {
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/*
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* DDR frequency is PHY_ROOT_CLK
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* PHY_ROOT_CLK = Fdpll/2/M2
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*/
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divider = 2;
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}
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ddr_clk = ddr_clk / divider / core_dpll_params->m2;
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ddr_clk *= 1000; /* convert to Hz */
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debug("ddr_clk %d\n ", ddr_clk);
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return ddr_clk;
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}
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/*
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* Lock MPU dpll
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*
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* Resulting MPU frequencies:
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* 4430 ES1.0 : 600 MHz
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* 4430 ES2.x : 792 MHz (OPP Turbo)
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* 4460 : 920 MHz (OPP Turbo) - DCC disabled
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*/
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void configure_mpu_dpll(void)
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{
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const struct dpll_params *params;
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struct dpll_regs *mpu_dpll_regs;
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u32 omap_rev;
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omap_rev = omap_revision();
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/*
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* DCC and clock divider settings for 4460.
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* DCC is required, if more than a certain frequency is required.
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* For, 4460 > 1GHZ.
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* 5430 > 1.4GHZ.
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*/
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if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
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mpu_dpll_regs =
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(struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
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bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
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clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
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MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
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setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
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MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
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clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
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CM_CLKSEL_DCC_EN_MASK);
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}
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params = get_mpu_dpll_params(*dplls_data);
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do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
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debug("MPU DPLL locked\n");
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}
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#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \
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defined(CONFIG_USB_MUSB_OMAP2PLUS)
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static void setup_usb_dpll(void)
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{
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const struct dpll_params *params;
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u32 sys_clk_khz, sd_div, num, den;
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sys_clk_khz = get_sys_clk_freq() / 1000;
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/*
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* USB:
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* USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
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* DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
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* - where CLKINP is sys_clk in MHz
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* Use CLKINP in KHz and adjust the denominator accordingly so
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* that we have enough accuracy and at the same time no overflow
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*/
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params = get_usb_dpll_params(*dplls_data);
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num = params->m * sys_clk_khz;
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den = (params->n + 1) * 250 * 1000;
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num += den - 1;
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sd_div = num / den;
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clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
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CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
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sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
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/* Now setup the dpll with the regular function */
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do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
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}
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#endif
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static void setup_dplls(void)
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{
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u32 temp;
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const struct dpll_params *params;
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struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
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debug("setup_dplls\n");
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/* CORE dpll */
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params = get_core_dpll_params(*dplls_data); /* default - safest */
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/*
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* Do not lock the core DPLL now. Just set it up.
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* Core DPLL will be locked after setting up EMIF
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* using the FREQ_UPDATE method(freq_update_core())
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*/
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if (emif_sdram_type(readl(&emif->emif_sdram_config)) ==
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EMIF_SDRAM_TYPE_LPDDR2)
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do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
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DPLL_NO_LOCK, "core");
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else
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do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
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DPLL_LOCK, "core");
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/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
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temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
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(CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
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(CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
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writel(temp, (*prcm)->cm_clksel_core);
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debug("Core DPLL configured\n");
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|
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/* lock PER dpll */
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params = get_per_dpll_params(*dplls_data);
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do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
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params, DPLL_LOCK, "per");
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debug("PER DPLL locked\n");
|
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|
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/* MPU dpll */
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configure_mpu_dpll();
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|
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#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \
|
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defined(CONFIG_USB_MUSB_OMAP2PLUS)
|
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setup_usb_dpll();
|
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#endif
|
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params = get_ddr_dpll_params(*dplls_data);
|
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do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
|
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params, DPLL_LOCK, "ddr");
|
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|
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#ifdef CONFIG_DRIVER_TI_CPSW
|
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params = get_gmac_dpll_params(*dplls_data);
|
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do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params,
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DPLL_LOCK, "gmac");
|
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#endif
|
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}
|
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|
|
u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
|
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{
|
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u32 offset_code;
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|
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volt_offset -= pmic->base_offset;
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|
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offset_code = (volt_offset + pmic->step - 1) / pmic->step;
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|
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/*
|
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* Offset codes 1-6 all give the base voltage in Palmas
|
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* Offset code 0 switches OFF the SMPS
|
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*/
|
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return offset_code + pmic->start_code;
|
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}
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|
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void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
|
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{
|
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u32 offset_code;
|
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u32 offset = volt_mv;
|
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int ret = 0;
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|
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if (!volt_mv)
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return;
|
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|
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pmic->pmic_bus_init();
|
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/* See if we can first get the GPIO if needed */
|
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if (pmic->gpio_en)
|
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ret = gpio_request(pmic->gpio, "PMIC_GPIO");
|
|
|
|
if (ret < 0) {
|
|
printf("%s: gpio %d request failed %d\n", __func__,
|
|
pmic->gpio, ret);
|
|
return;
|
|
}
|
|
|
|
/* Pull the GPIO low to select SET0 register, while we program SET1 */
|
|
if (pmic->gpio_en)
|
|
gpio_direction_output(pmic->gpio, 0);
|
|
|
|
/* convert to uV for better accuracy in the calculations */
|
|
offset *= 1000;
|
|
|
|
offset_code = get_offset_code(offset, pmic);
|
|
|
|
debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
|
|
offset_code);
|
|
|
|
if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
|
|
printf("Scaling voltage failed for 0x%x\n", vcore_reg);
|
|
if (pmic->gpio_en)
|
|
gpio_direction_output(pmic->gpio, 1);
|
|
}
|
|
|
|
int __weak get_voltrail_opp(int rail_offset)
|
|
{
|
|
/*
|
|
* By default return OPP_NOM for all voltage rails.
|
|
*/
|
|
return OPP_NOM;
|
|
}
|
|
|
|
static u32 optimize_vcore_voltage(struct volts const *v, int opp)
|
|
{
|
|
u32 val;
|
|
|
|
if (!v->value[opp])
|
|
return 0;
|
|
if (!v->efuse.reg[opp])
|
|
return v->value[opp];
|
|
|
|
switch (v->efuse.reg_bits) {
|
|
case 16:
|
|
val = readw(v->efuse.reg[opp]);
|
|
break;
|
|
case 32:
|
|
val = readl(v->efuse.reg[opp]);
|
|
break;
|
|
default:
|
|
printf("Error: efuse 0x%08x bits=%d unknown\n",
|
|
v->efuse.reg[opp], v->efuse.reg_bits);
|
|
return v->value[opp];
|
|
}
|
|
|
|
if (!val) {
|
|
printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
|
|
v->efuse.reg[opp], v->efuse.reg_bits, v->value[opp]);
|
|
return v->value[opp];
|
|
}
|
|
|
|
debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
|
|
__func__, v->efuse.reg[opp], v->efuse.reg_bits, v->value[opp],
|
|
val);
|
|
return val;
|
|
}
|
|
|
|
#ifdef CONFIG_IODELAY_RECALIBRATION
|
|
void __weak recalibrate_iodelay(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Setup the voltages for the main SoC core power domains.
|
|
* We start with the maximum voltages allowed here, as set in the corresponding
|
|
* vcores_data struct, and then scale (usually down) to the fused values that
|
|
* are retrieved from the SoC. The scaling happens only if the efuse.reg fields
|
|
* are initialised.
|
|
* Rail grouping is supported for the DRA7xx SoCs only, therefore the code is
|
|
* compiled conditionally. Note that the new code writes the scaled (or zeroed)
|
|
* values back to the vcores_data struct for eventual reuse. Zero values mean
|
|
* that the corresponding rails are not controlled separately, and are not sent
|
|
* to the PMIC.
|
|
*/
|
|
void scale_vcores(struct vcores_data const *vcores)
|
|
{
|
|
int i, opp, j, ol;
|
|
struct volts *pv = (struct volts *)vcores;
|
|
struct volts *px;
|
|
|
|
for (i=0; i<(sizeof(struct vcores_data)/sizeof(struct volts)); i++) {
|
|
opp = get_voltrail_opp(i);
|
|
debug("%d -> ", pv->value[opp]);
|
|
|
|
if (pv->value[opp]) {
|
|
/* Handle non-empty members only */
|
|
pv->value[opp] = optimize_vcore_voltage(pv, opp);
|
|
px = (struct volts *)vcores;
|
|
j = 0;
|
|
while (px < pv) {
|
|
/*
|
|
* Scan already handled non-empty members to see
|
|
* if we have a group and find the max voltage,
|
|
* which is set to the first occurance of the
|
|
* particular SMPS; the other group voltages are
|
|
* zeroed.
|
|
*/
|
|
ol = get_voltrail_opp(j);
|
|
if (px->value[ol] &&
|
|
(pv->pmic->i2c_slave_addr ==
|
|
px->pmic->i2c_slave_addr) &&
|
|
(pv->addr == px->addr)) {
|
|
/* Same PMIC, same SMPS */
|
|
if (pv->value[opp] > px->value[ol])
|
|
px->value[ol] = pv->value[opp];
|
|
|
|
pv->value[opp] = 0;
|
|
}
|
|
px++;
|
|
j++;
|
|
}
|
|
}
|
|
debug("%d\n", pv->value[opp]);
|
|
pv++;
|
|
}
|
|
|
|
opp = get_voltrail_opp(VOLT_CORE);
|
|
debug("cor: %d\n", vcores->core.value[opp]);
|
|
do_scale_vcore(vcores->core.addr, vcores->core.value[opp],
|
|
vcores->core.pmic);
|
|
/*
|
|
* IO delay recalibration should be done immediately after
|
|
* adjusting AVS voltages for VDD_CORE_L.
|
|
* Respective boards should call __recalibrate_iodelay()
|
|
* with proper mux, virtual and manual mode configurations.
|
|
*/
|
|
#ifdef CONFIG_IODELAY_RECALIBRATION
|
|
recalibrate_iodelay();
|
|
#endif
|
|
|
|
opp = get_voltrail_opp(VOLT_MPU);
|
|
debug("mpu: %d\n", vcores->mpu.value[opp]);
|
|
do_scale_vcore(vcores->mpu.addr, vcores->mpu.value[opp],
|
|
vcores->mpu.pmic);
|
|
/* Configure MPU ABB LDO after scale */
|
|
abb_setup(vcores->mpu.efuse.reg[opp],
|
|
(*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
|
|
(*prcm)->prm_abbldo_mpu_setup,
|
|
(*prcm)->prm_abbldo_mpu_ctrl,
|
|
(*prcm)->prm_irqstatus_mpu_2,
|
|
vcores->mpu.abb_tx_done_mask,
|
|
OMAP_ABB_FAST_OPP);
|
|
|
|
opp = get_voltrail_opp(VOLT_MM);
|
|
debug("mm: %d\n", vcores->mm.value[opp]);
|
|
do_scale_vcore(vcores->mm.addr, vcores->mm.value[opp],
|
|
vcores->mm.pmic);
|
|
/* Configure MM ABB LDO after scale */
|
|
abb_setup(vcores->mm.efuse.reg[opp],
|
|
(*ctrl)->control_wkup_ldovbb_mm_voltage_ctrl,
|
|
(*prcm)->prm_abbldo_mm_setup,
|
|
(*prcm)->prm_abbldo_mm_ctrl,
|
|
(*prcm)->prm_irqstatus_mpu,
|
|
vcores->mm.abb_tx_done_mask,
|
|
OMAP_ABB_FAST_OPP);
|
|
|
|
opp = get_voltrail_opp(VOLT_GPU);
|
|
debug("gpu: %d\n", vcores->gpu.value[opp]);
|
|
do_scale_vcore(vcores->gpu.addr, vcores->gpu.value[opp],
|
|
vcores->gpu.pmic);
|
|
/* Configure GPU ABB LDO after scale */
|
|
abb_setup(vcores->gpu.efuse.reg[opp],
|
|
(*ctrl)->control_wkup_ldovbb_gpu_voltage_ctrl,
|
|
(*prcm)->prm_abbldo_gpu_setup,
|
|
(*prcm)->prm_abbldo_gpu_ctrl,
|
|
(*prcm)->prm_irqstatus_mpu,
|
|
vcores->gpu.abb_tx_done_mask,
|
|
OMAP_ABB_FAST_OPP);
|
|
|
|
opp = get_voltrail_opp(VOLT_EVE);
|
|
debug("eve: %d\n", vcores->eve.value[opp]);
|
|
do_scale_vcore(vcores->eve.addr, vcores->eve.value[opp],
|
|
vcores->eve.pmic);
|
|
/* Configure EVE ABB LDO after scale */
|
|
abb_setup(vcores->eve.efuse.reg[opp],
|
|
(*ctrl)->control_wkup_ldovbb_eve_voltage_ctrl,
|
|
(*prcm)->prm_abbldo_eve_setup,
|
|
(*prcm)->prm_abbldo_eve_ctrl,
|
|
(*prcm)->prm_irqstatus_mpu,
|
|
vcores->eve.abb_tx_done_mask,
|
|
OMAP_ABB_FAST_OPP);
|
|
|
|
opp = get_voltrail_opp(VOLT_IVA);
|
|
debug("iva: %d\n", vcores->iva.value[opp]);
|
|
do_scale_vcore(vcores->iva.addr, vcores->iva.value[opp],
|
|
vcores->iva.pmic);
|
|
/* Configure IVA ABB LDO after scale */
|
|
abb_setup(vcores->iva.efuse.reg[opp],
|
|
(*ctrl)->control_wkup_ldovbb_iva_voltage_ctrl,
|
|
(*prcm)->prm_abbldo_iva_setup,
|
|
(*prcm)->prm_abbldo_iva_ctrl,
|
|
(*prcm)->prm_irqstatus_mpu,
|
|
vcores->iva.abb_tx_done_mask,
|
|
OMAP_ABB_FAST_OPP);
|
|
}
|
|
|
|
static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
|
|
{
|
|
clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
|
|
enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
|
|
debug("Enable clock domain - %x\n", clkctrl_reg);
|
|
}
|
|
|
|
static inline void disable_clock_domain(u32 const clkctrl_reg)
|
|
{
|
|
clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
|
|
CD_CLKCTRL_CLKTRCTRL_SW_SLEEP <<
|
|
CD_CLKCTRL_CLKTRCTRL_SHIFT);
|
|
debug("Disable clock domain - %x\n", clkctrl_reg);
|
|
}
|
|
|
|
static inline void wait_for_clk_enable(u32 clkctrl_addr)
|
|
{
|
|
u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
|
|
u32 bound = LDELAY;
|
|
|
|
while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
|
|
(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
|
|
|
|
clkctrl = readl(clkctrl_addr);
|
|
idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
|
|
MODULE_CLKCTRL_IDLEST_SHIFT;
|
|
if (--bound == 0) {
|
|
printf("Clock enable failed for 0x%x idlest 0x%x\n",
|
|
clkctrl_addr, clkctrl);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
|
|
u32 wait_for_enable)
|
|
{
|
|
clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
|
|
enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
|
|
debug("Enable clock module - %x\n", clkctrl_addr);
|
|
if (wait_for_enable)
|
|
wait_for_clk_enable(clkctrl_addr);
|
|
}
|
|
|
|
static inline void wait_for_clk_disable(u32 clkctrl_addr)
|
|
{
|
|
u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
|
|
u32 bound = LDELAY;
|
|
|
|
while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
|
|
clkctrl = readl(clkctrl_addr);
|
|
idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
|
|
MODULE_CLKCTRL_IDLEST_SHIFT;
|
|
if (--bound == 0) {
|
|
printf("Clock disable failed for 0x%x idlest 0x%x\n",
|
|
clkctrl_addr, clkctrl);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
static inline void disable_clock_module(u32 const clkctrl_addr,
|
|
u32 wait_for_disable)
|
|
{
|
|
clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
|
|
MODULE_CLKCTRL_MODULEMODE_SW_DISABLE <<
|
|
MODULE_CLKCTRL_MODULEMODE_SHIFT);
|
|
debug("Disable clock module - %x\n", clkctrl_addr);
|
|
if (wait_for_disable)
|
|
wait_for_clk_disable(clkctrl_addr);
|
|
}
|
|
|
|
void freq_update_core(void)
|
|
{
|
|
u32 freq_config1 = 0;
|
|
const struct dpll_params *core_dpll_params;
|
|
u32 omap_rev = omap_revision();
|
|
|
|
core_dpll_params = get_core_dpll_params(*dplls_data);
|
|
/* Put EMIF clock domain in sw wakeup mode */
|
|
enable_clock_domain((*prcm)->cm_memif_clkstctrl,
|
|
CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
|
|
wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
|
|
wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
|
|
|
|
freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
|
|
SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
|
|
|
|
freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
|
|
SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
|
|
|
|
freq_config1 |= (core_dpll_params->m2 <<
|
|
SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
|
|
SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
|
|
|
|
writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
|
|
if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
|
|
(u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
|
|
puts("FREQ UPDATE procedure failed!!");
|
|
hang();
|
|
}
|
|
|
|
/*
|
|
* Putting EMIF in HW_AUTO is seen to be causing issues with
|
|
* EMIF clocks and the master DLL. Keep EMIF in SW_WKUP
|
|
* in OMAP5430 ES1.0 silicon
|
|
*/
|
|
if (omap_rev != OMAP5430_ES1_0) {
|
|
/* Put EMIF clock domain back in hw auto mode */
|
|
enable_clock_domain((*prcm)->cm_memif_clkstctrl,
|
|
CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
|
|
wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
|
|
wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
|
|
}
|
|
}
|
|
|
|
void bypass_dpll(u32 const base)
|
|
{
|
|
do_bypass_dpll(base);
|
|
wait_for_bypass(base);
|
|
}
|
|
|
|
void lock_dpll(u32 const base)
|
|
{
|
|
do_lock_dpll(base);
|
|
wait_for_lock(base);
|
|
}
|
|
|
|
static void setup_clocks_for_console(void)
|
|
{
|
|
/* Do not add any spl_debug prints in this function */
|
|
clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
|
|
CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
|
|
CD_CLKCTRL_CLKTRCTRL_SHIFT);
|
|
|
|
/* Enable all UARTs - console will be on one of them */
|
|
clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
|
|
MODULE_CLKCTRL_MODULEMODE_MASK,
|
|
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
|
|
MODULE_CLKCTRL_MODULEMODE_SHIFT);
|
|
|
|
clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
|
|
MODULE_CLKCTRL_MODULEMODE_MASK,
|
|
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
|
|
MODULE_CLKCTRL_MODULEMODE_SHIFT);
|
|
|
|
clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
|
|
MODULE_CLKCTRL_MODULEMODE_MASK,
|
|
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
|
|
MODULE_CLKCTRL_MODULEMODE_SHIFT);
|
|
|
|
clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl,
|
|
MODULE_CLKCTRL_MODULEMODE_MASK,
|
|
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
|
|
MODULE_CLKCTRL_MODULEMODE_SHIFT);
|
|
|
|
clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
|
|
CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
|
|
CD_CLKCTRL_CLKTRCTRL_SHIFT);
|
|
}
|
|
|
|
void do_enable_clocks(u32 const *clk_domains,
|
|
u32 const *clk_modules_hw_auto,
|
|
u32 const *clk_modules_explicit_en,
|
|
u8 wait_for_enable)
|
|
{
|
|
u32 i, max = 100;
|
|
|
|
/* Put the clock domains in SW_WKUP mode */
|
|
for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
|
|
enable_clock_domain(clk_domains[i],
|
|
CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
|
|
}
|
|
|
|
/* Clock modules that need to be put in HW_AUTO */
|
|
for (i = 0; (i < max) && clk_modules_hw_auto &&
|
|
clk_modules_hw_auto[i]; i++) {
|
|
enable_clock_module(clk_modules_hw_auto[i],
|
|
MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
|
|
wait_for_enable);
|
|
};
|
|
|
|
/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
|
|
for (i = 0; (i < max) && clk_modules_explicit_en &&
|
|
clk_modules_explicit_en[i]; i++) {
|
|
enable_clock_module(clk_modules_explicit_en[i],
|
|
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
|
|
wait_for_enable);
|
|
};
|
|
|
|
/* Put the clock domains in HW_AUTO mode now */
|
|
for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
|
|
enable_clock_domain(clk_domains[i],
|
|
CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
|
|
}
|
|
}
|
|
|
|
void do_disable_clocks(u32 const *clk_domains,
|
|
u32 const *clk_modules_disable,
|
|
u8 wait_for_disable)
|
|
{
|
|
u32 i, max = 100;
|
|
|
|
|
|
/* Clock modules that need to be put in SW_DISABLE */
|
|
for (i = 0; (i < max) && clk_modules_disable[i]; i++)
|
|
disable_clock_module(clk_modules_disable[i],
|
|
wait_for_disable);
|
|
|
|
/* Put the clock domains in SW_SLEEP mode */
|
|
for (i = 0; (i < max) && clk_domains[i]; i++)
|
|
disable_clock_domain(clk_domains[i]);
|
|
}
|
|
|
|
/**
|
|
* setup_early_clocks() - Setup early clocks needed for SoC
|
|
*
|
|
* Setup clocks for console, SPL basic initialization clocks and initialize
|
|
* the timer. This is invoked prior prcm_init.
|
|
*/
|
|
void setup_early_clocks(void)
|
|
{
|
|
switch (omap_hw_init_context()) {
|
|
case OMAP_INIT_CONTEXT_SPL:
|
|
case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
|
|
case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
|
|
setup_clocks_for_console();
|
|
enable_basic_clocks();
|
|
timer_init();
|
|
/* Fall through */
|
|
}
|
|
}
|
|
|
|
void prcm_init(void)
|
|
{
|
|
switch (omap_hw_init_context()) {
|
|
case OMAP_INIT_CONTEXT_SPL:
|
|
case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
|
|
case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
|
|
scale_vcores(*omap_vcores);
|
|
setup_dplls();
|
|
setup_warmreset_time();
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
|
|
enable_basic_uboot_clocks();
|
|
}
|
|
|
|
void gpi2c_init(void)
|
|
{
|
|
static int gpi2c = 1;
|
|
|
|
if (gpi2c) {
|
|
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
|
|
CONFIG_SYS_OMAP24_I2C_SLAVE);
|
|
gpi2c = 0;
|
|
}
|
|
}
|