mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
92 lines
2.5 KiB
C
92 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* SH7780 PCI Controller (PCIC) for U-Boot.
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* (C) Dustin McIntire (dustin@sensoria.com)
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* (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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* (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/pci.h>
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#include <asm/io.h>
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#define SH7780_VENDOR_ID 0x1912
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#define SH7780_DEVICE_ID 0x0002
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#define SH7780_PCICR_PREFIX 0xA5000000
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#define SH7780_PCICR_PFCS 0x00000800
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#define SH7780_PCICR_FTO 0x00000400
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#define SH7780_PCICR_PFE 0x00000200
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#define SH7780_PCICR_TBS 0x00000100
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#define SH7780_PCICR_ARBM 0x00000040
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#define SH7780_PCICR_IOCS 0x00000004
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#define SH7780_PCICR_PRST 0x00000002
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#define SH7780_PCICR_CFIN 0x00000001
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#define p4_in(addr) (*(vu_long *)addr)
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#define p4_out(data, addr) (*(vu_long *)addr) = (data)
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#define p4_inw(addr) (*(vu_short *)addr)
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#define p4_outw(data, addr) (*(vu_short *)addr) = (data)
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int pci_sh4_read_config_dword(struct pci_controller *hose,
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pci_dev_t dev, int offset, u32 *value)
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{
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u32 par_data = 0x80000000 | dev;
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p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR);
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*value = p4_in(SH7780_PCIPDR);
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return 0;
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}
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int pci_sh4_write_config_dword(struct pci_controller *hose,
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pci_dev_t dev, int offset, u32 value)
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{
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u32 par_data = 0x80000000 | dev;
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p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR);
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p4_out(value, SH7780_PCIPDR);
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return 0;
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}
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int pci_sh7780_init(struct pci_controller *hose)
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{
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p4_out(0x01, SH7780_PCIECR);
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if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID
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&& p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID) {
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printf("PCI: Unknown PCI host bridge.\n");
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return -1;
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}
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printf("PCI: SH7780 PCI host bridge found.\n");
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/* Toggle PCI reset pin */
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p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_PRST), SH7780_PCICR);
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udelay(100000);
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p4_out(SH7780_PCICR_PREFIX, SH7780_PCICR);
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p4_outw(0x0047, SH7780_PCICMD);
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p4_out(CONFIG_SH7780_PCI_LSR, SH7780_PCILSR0);
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p4_out(CONFIG_SH7780_PCI_LAR, SH7780_PCILAR0);
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p4_out(0x00000000, SH7780_PCILSR1);
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p4_out(0, SH7780_PCILAR1);
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p4_out(CONFIG_SH7780_PCI_BAR, SH7780_PCIMBAR0);
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p4_out(0x00000000, SH7780_PCIMBAR1);
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p4_out(0xFD000000, SH7780_PCIMBR0);
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p4_out(0x00FC0000, SH7780_PCIMBMR0);
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/* if use Operand Cache then enable PCICSCR Soonp bits. */
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p4_out(0x08000000, SH7780_PCICSAR0);
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p4_out(0x0000001B, SH7780_PCICSCR0); /* Snoop bit :On */
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p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_CFIN | SH7780_PCICR_ARBM
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| SH7780_PCICR_FTO | SH7780_PCICR_PFCS | SH7780_PCICR_PFE),
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SH7780_PCICR);
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pci_sh4_init(hose);
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return 0;
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}
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