Siva Durga Prasad Paladugu f60c6fbbc6 ARM: zynq: slcr: Dont modify the reserved bits ... Set only the 0-3 bits of the FPGA_RST_CTRL register as other bits should not be set to 1. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Nathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>		2015-01-26 08:55:57 +01:00
..
clk.c	zynq: Update CLK in bdinfo	2014-02-19 09:41:22 +01:00
config.mk	ARM: zynq: Enable the Neon instructions	2015-01-26 08:55:31 +01:00
cpu.c	ARM: zynq: Remove empty line	2015-01-26 08:55:57 +01:00
ddrc.c	ARM: zynq: ddrc: Setup half of memory only for ECC case	2015-01-26 08:55:57 +01:00
Kconfig	kconfig: zynq: Add ZYBO board	2014-11-11 11:02:52 +01:00
lowlevel_init.S	ARM: zynq: Enable the Neon instructions	2015-01-26 08:55:31 +01:00
Makefile	ARM: zynq: Enable the Neon instructions	2015-01-26 08:55:31 +01:00
slcr.c	ARM: zynq: slcr: Dont modify the reserved bits	2015-01-26 08:55:57 +01:00
spl.c	Rename some defines containing FAT in their name to be filesystem generic	2014-10-27 11:04:01 -04:00
timer.c	arm: zynq: correct the argument to lldiv	2014-02-19 09:41:22 +01:00
u-boot-spl.lds	zynq: spl: Add vectors section to linker script	2014-08-08 11:27:29 +02:00
u-boot.lds	arm: zynq: fix a bug in Zynq linker script	2014-06-17 12:28:26 +02:00