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f5a432959a
The original clock support for MMC/SD cards on the RK3368 suffered from a tendency to select a divider less-or-equal to the the one giving the requested clock-rate: this can lead to higher-than-expected (or rather: higher than supported) clock rates for the MMC/SD communiction. This change rewrites the MMC/SD clock generation to: * always generate a clock less-than-or-equal to the requested clock * support reparenting among the CPLL, GPLL and OSC24M parents to generate the highest clock that does not exceed the requested rate In addition to this, the Linux DTS uses HCLK_MMC/HCLK_SDMMC instead of SCLK_MMC/SCLK_SDMMC: to match this (and to ensure that clock setup always works), we adjust the driver appropriately. This includes the changes from: - rockchip: clk: rk3368: convert MMC_PLL_SEL_* definitions to shifted-value form Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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| .. | ||
| aspeed | ||
| at91 | ||
| exynos | ||
| renesas | ||
| rockchip | ||
| tegra | ||
| uniphier | ||
| clk_bcm6345.c | ||
| clk_boston.c | ||
| clk_fixed_rate.c | ||
| clk_pic32.c | ||
| clk_sandbox_test.c | ||
| clk_sandbox.c | ||
| clk_stm32f7.c | ||
| clk_zynq.c | ||
| clk_zynqmp.c | ||
| clk-uclass.c | ||
| Kconfig | ||
| Makefile | ||