mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
f59e69cbd3
The SEC driver code has been cleaned up to work for 64 bit physical addresses and systems where endianess of SEC block is different from the Core. Changes: 1. Descriptor created on Core is modified as per SEC block endianness before the job is submitted. 2. The read/write of physical addresses to Job Rings will be depend on endianness of SEC block as 32 bit low and high part of the 64 bit address will vary. 3. The 32 bit low and high part of the 64 bit address in descriptor will vary depending on endianness of SEC. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
290 lines
8.5 KiB
C
290 lines
8.5 KiB
C
/*
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* Common internal memory map for some Freescale SoCs
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*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_SEC_H
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#define __FSL_SEC_H
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#include <common.h>
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#include <asm/io.h>
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#ifdef CONFIG_SYS_FSL_SEC_LE
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#define sec_in32(a) in_le32(a)
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#define sec_out32(a, v) out_le32(a, v)
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#define sec_in16(a) in_le16(a)
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#define sec_clrbits32 clrbits_le32
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#define sec_setbits32 setbits_le32
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#elif defined(CONFIG_SYS_FSL_SEC_BE)
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#define sec_in32(a) in_be32(a)
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#define sec_out32(a, v) out_be32(a, v)
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#define sec_in16(a) in_be16(a)
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#define sec_clrbits32 clrbits_be32
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#define sec_setbits32 setbits_be32
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#else
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#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
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#endif
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/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
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#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
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/* RNG4 TRNG test registers */
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struct rng4tst {
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#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
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#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
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both entropy shifter and
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statistical checker */
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#define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both
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entropy shifter and
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statistical checker */
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#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
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entropy shifter, raw data
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in statistical checker */
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#define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */
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u32 rtmctl; /* misc. control register */
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u32 rtscmisc; /* statistical check misc. register */
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u32 rtpkrrng; /* poker range register */
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#define RTSDCTL_ENT_DLY_MIN 3200
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#define RTSDCTL_ENT_DLY_MAX 12800
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union {
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u32 rtpkrmax; /* PRGM=1: poker max. limit register */
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u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
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};
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#define RTSDCTL_ENT_DLY_SHIFT 16
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#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
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u32 rtsdctl; /* seed control register */
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union {
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u32 rtsblim; /* PRGM=1: sparse bit limit register */
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u32 rttotsam; /* PRGM=0: total samples register */
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};
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u32 rtfreqmin; /* frequency count min. limit register */
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#define RTFRQMAX_DISABLE (1 << 20)
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union {
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u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */
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u32 rtfreqcnt; /* PRGM=0: freq. count register */
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};
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u32 rsvd1[40];
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#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
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u32 rdsta; /*RNG DRNG Status Register*/
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u32 rsvd2[15];
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};
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typedef struct ccsr_sec {
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u32 res0;
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u32 mcfgr; /* Master CFG Register */
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u8 res1[0x4];
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u32 scfgr;
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struct {
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u32 ms; /* Job Ring LIODN Register, MS */
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u32 ls; /* Job Ring LIODN Register, LS */
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} jrliodnr[4];
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u8 res2[0x2c];
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u32 jrstartr; /* Job Ring Start Register */
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struct {
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u32 ms; /* RTIC LIODN Register, MS */
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u32 ls; /* RTIC LIODN Register, LS */
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} rticliodnr[4];
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u8 res3[0x1c];
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u32 decorr; /* DECO Request Register */
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struct {
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u32 ms; /* DECO LIODN Register, MS */
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u32 ls; /* DECO LIODN Register, LS */
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} decoliodnr[8];
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u8 res4[0x40];
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u32 dar; /* DECO Avail Register */
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u32 drr; /* DECO Reset Register */
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u8 res5[0x4d8];
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struct rng4tst rng; /* RNG Registers */
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u8 res11[0x8a0];
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u32 crnr_ms; /* CHA Revision Number Register, MS */
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u32 crnr_ls; /* CHA Revision Number Register, LS */
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u32 ctpr_ms; /* Compile Time Parameters Register, MS */
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u32 ctpr_ls; /* Compile Time Parameters Register, LS */
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u8 res6[0x10];
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u32 far_ms; /* Fault Address Register, MS */
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u32 far_ls; /* Fault Address Register, LS */
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u32 falr; /* Fault Address LIODN Register */
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u32 fadr; /* Fault Address Detail Register */
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u8 res7[0x4];
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u32 csta; /* CAAM Status Register */
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u8 res8[0x8];
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u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
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u32 ccbvid; /* CHA Cluster Block Version ID Register */
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u32 chavid_ms; /* CHA Version ID Register, MS */
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u32 chavid_ls; /* CHA Version ID Register, LS */
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u32 chanum_ms; /* CHA Number Register, MS */
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u32 chanum_ls; /* CHA Number Register, LS */
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u32 secvid_ms; /* SEC Version ID Register, MS */
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u32 secvid_ls; /* SEC Version ID Register, LS */
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u8 res9[0x6020];
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u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
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u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
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u8 res10[0x8fd8];
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} ccsr_sec_t;
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#define SEC_CTPR_MS_AXI_LIODN 0x08000000
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#define SEC_CTPR_MS_QI 0x02000000
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#define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
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#define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
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#define SEC_RVID_MA 0x0f000000
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#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
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#define SEC_CHANUM_MS_JRNUM_SHIFT 28
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#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
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#define SEC_CHANUM_MS_DECONUM_SHIFT 24
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#define SEC_SECVID_MS_IPID_MASK 0xffff0000
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#define SEC_SECVID_MS_IPID_SHIFT 16
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#define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
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#define SEC_SECVID_MS_MAJ_REV_SHIFT 8
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#define SEC_CCBVID_ERA_MASK 0xff000000
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#define SEC_CCBVID_ERA_SHIFT 24
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#define SEC_SCFGR_RDBENABLE 0x00000400
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#define SEC_SCFGR_VIRT_EN 0x00008000
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#define SEC_CHAVID_LS_RNG_SHIFT 16
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#define SEC_CHAVID_RNG_LS_MASK 0x000f0000
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#define CONFIG_JRSTARTR_JR0 0x00000001
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struct jr_regs {
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#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
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u32 irba_l;
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u32 irba_h;
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#else
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u32 irba_h;
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u32 irba_l;
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#endif
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u32 rsvd1;
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u32 irs;
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u32 rsvd2;
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u32 irsa;
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u32 rsvd3;
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u32 irja;
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#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
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u32 orba_l;
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u32 orba_h;
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#else
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u32 orba_h;
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u32 orba_l;
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#endif
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u32 rsvd4;
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u32 ors;
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u32 rsvd5;
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u32 orjr;
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u32 rsvd6;
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u32 orsf;
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u32 rsvd7;
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u32 jrsta;
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u32 rsvd8;
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u32 jrint;
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u32 jrcfg0;
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u32 jrcfg1;
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u32 rsvd9;
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u32 irri;
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u32 rsvd10;
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u32 orwi;
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u32 rsvd11;
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u32 jrcr;
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};
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/*
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* Scatter Gather Entry - Specifies the the Scatter Gather Format
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* related information
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*/
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struct sg_entry {
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#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
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uint32_t addr_lo; /* Memory Address - lo */
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uint32_t addr_hi; /* Memory Address of start of buffer - hi */
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#else
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uint32_t addr_hi; /* Memory Address of start of buffer - hi */
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uint32_t addr_lo; /* Memory Address - lo */
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#endif
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uint32_t len_flag; /* Length of the data in the frame */
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#define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
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#define SG_ENTRY_EXTENSION_BIT 0x80000000
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#define SG_ENTRY_FINAL_BIT 0x40000000
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uint32_t bpid_offset;
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#define SG_ENTRY_BPID_MASK 0x00FF0000
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#define SG_ENTRY_BPID_SHIFT 16
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#define SG_ENTRY_OFFSET_MASK 0x00001FFF
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#define SG_ENTRY_OFFSET_SHIFT 0
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};
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#ifdef CONFIG_MX6
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/* CAAM Job Ring 0 Registers */
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/* Secure Memory Partition Owner register */
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#define SMCSJR_PO (3 << 6)
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/* JR Allocation Error */
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#define SMCSJR_AERR (3 << 12)
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/* Secure memory partition 0 page 0 owner register */
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#define CAAM_SMPO_0 CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC
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/* Secure memory command register */
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#define CAAM_SMCJR0 CONFIG_SYS_FSL_SEC_ADDR + 0x10f4
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/* Secure memory command status register */
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#define CAAM_SMCSJR0 CONFIG_SYS_FSL_SEC_ADDR + 0x10fc
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/* Secure memory access permissions register */
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#define CAAM_SMAPJR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1104 + y*16)
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/* Secure memory access group 2 register */
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#define CAAM_SMAG2JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1108 + y*16)
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/* Secure memory access group 1 register */
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#define CAAM_SMAG1JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x110C + y*16)
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/* Commands and macros for secure memory */
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#define CMD_PAGE_ALLOC 0x1
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#define CMD_PAGE_DEALLOC 0x2
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#define CMD_PART_DEALLOC 0x3
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#define CMD_INQUIRY 0x5
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#define CMD_COMPLETE (3 << 14)
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#define PAGE_AVAILABLE 0
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#define PAGE_OWNED (3 << 6)
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#define PAGE(x) (x << 16)
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#define PARTITION(x) (x << 8)
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#define PARTITION_OWNER(x) (0x3 << (x*2))
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/* Address of secure 4kbyte pages */
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#define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR
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#define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000)
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#define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000)
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#define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000)
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#define JR_MID 2 /* Matches ROM configuration */
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#define KS_G1 (1 << JR_MID) /* CAAM only */
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#define PERM 0x0000B008 /* Clear on release, lock SMAP
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* lock SMAG group 1 Blob */
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#define BLOB_SIZE(x) (x + 32 + 16) /* Blob buffer size */
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/* HAB WRAPPED KEY header */
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#define WRP_HDR_SIZE 0x08
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#define HDR_TAG 0x81
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#define HDR_PAR 0x41
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/* HAB WRAPPED KEY Data */
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#define HAB_MOD 0x66
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#define HAB_ALG 0x55
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#define HAB_FLG 0x00
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/* Partition and Page IDs */
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#define PARTITION_1 1
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#define PAGE_1 1
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#define ERROR_IN_PAGE_ALLOC 1
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#define ECONSTRJDESC -1
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#endif
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int sec_init(void);
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/* blob_dek:
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* Encapsulates the src in a secure blob and stores it dst
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* @src: reference to the plaintext
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* @dst: reference to the output adrress
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* @len: size in bytes of src
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* @return: 0 on success, error otherwise
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*/
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int blob_dek(const u8 *src, u8 *dst, u8 len);
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#endif
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#endif /* __FSL_SEC_H */
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