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https://github.com/brain-hackers/u-boot-brain
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f59e69cbd3
The SEC driver code has been cleaned up to work for 64 bit physical addresses and systems where endianess of SEC block is different from the Core. Changes: 1. Descriptor created on Core is modified as per SEC block endianness before the job is submitted. 2. The read/write of physical addresses to Job Rings will be depend on endianness of SEC block as 32 bit low and high part of the 64 bit address will vary. 3. The 32 bit low and high part of the 64 bit address in descriptor will vary depending on endianness of SEC. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
99 lines
2.3 KiB
C
99 lines
2.3 KiB
C
/*
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* Copyright 2008-2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#ifndef __JR_H
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#define __JR_H
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#include <linux/compiler.h>
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#define JR_SIZE 4
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/* Timeout currently defined as 90 sec */
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#define CONFIG_SEC_DEQ_TIMEOUT 90000000U
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#define DEFAULT_JR_ID 0
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#define DEFAULT_JR_LIODN 0
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#define DEFAULT_IRQ 0 /* Interrupts not to be configured */
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#define MCFGR_SWRST ((uint32_t)(1)<<31) /* Software Reset */
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#define MCFGR_DMA_RST ((uint32_t)(1)<<28) /* DMA Reset */
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#define MCFGR_PS_SHIFT 16
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#define MCFGR_AWCACHE_SHIFT 8
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#define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT)
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#define JR_INTMASK 0x00000001
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#define JRCR_RESET 0x01
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#define JRINT_ERR_HALT_INPROGRESS 0x4
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#define JRINT_ERR_HALT_MASK 0xc
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#define JRNSLIODN_SHIFT 16
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#define JRNSLIODN_MASK 0x0fff0000
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#define JRSLIODN_SHIFT 0
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#define JRSLIODN_MASK 0x00000fff
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#define JQ_DEQ_ERR -1
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#define JQ_DEQ_TO_ERR -2
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#define JQ_ENQ_ERR -3
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struct op_ring {
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phys_addr_t desc;
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uint32_t status;
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} __packed;
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struct jr_info {
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void (*callback)(uint32_t status, void *arg);
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phys_addr_t desc_phys_addr;
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uint32_t desc_len;
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uint32_t op_done;
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void *arg;
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};
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struct jobring {
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int jq_id;
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int irq;
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int liodn;
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/* Head is the index where software would enq the descriptor in
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* the i/p ring
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*/
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int head;
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/* Tail index would be used by s/w ehile enqueuing to determine if
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* there is any space left in the s/w maintained i/p rings
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*/
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/* Also in case of deq tail will be incremented only in case of
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* in-order job completion
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*/
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int tail;
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/* Read index of the output ring. It may not match with tail in case
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* of out of order completetion
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*/
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int read_idx;
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/* Write index to input ring. Would be always equal to head */
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int write_idx;
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/* Size of the rings. */
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int size;
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/* The ip and output rings have to be accessed by SEC. So the
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* pointers will ahve to point to the housekeeping region provided
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* by SEC
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*/
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/*Circular Ring of i/p descriptors */
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dma_addr_t *input_ring;
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/* Circular Ring of o/p descriptors */
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/* Circula Ring containing info regarding descriptors in i/p
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* and o/p ring
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*/
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/* This ring can be on the stack */
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struct jr_info info[JR_SIZE];
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struct op_ring *output_ring;
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};
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struct result {
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int done;
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uint32_t status;
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};
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void caam_jr_strstatus(u32 status);
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int run_descriptor_jr(uint32_t *desc);
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#endif
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