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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
617 lines
15 KiB
C
617 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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#include <clk.h>
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#include <dm.h>
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#include <malloc.h>
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#include <spi.h>
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#include <spi-mem.h>
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#include <watchdog.h>
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#include <asm/io.h>
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#include <asm/unaligned.h>
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#include <linux/bitfield.h>
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#include <linux/compat.h>
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#include <linux/delay.h>
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#define OCTEON_SPI_MAX_BYTES 9
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#define OCTEON_SPI_MAX_CLOCK_HZ 50000000
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#define OCTEON_SPI_NUM_CS 4
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#define OCTEON_SPI_CS_VALID(cs) ((cs) < OCTEON_SPI_NUM_CS)
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#define MPI_CFG 0x0000
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#define MPI_STS 0x0008
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#define MPI_TX 0x0010
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#define MPI_XMIT 0x0018
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#define MPI_WIDE_DAT 0x0040
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#define MPI_IO_CTL 0x0048
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#define MPI_DAT(X) (0x0080 + ((X) << 3))
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#define MPI_WIDE_BUF(X) (0x0800 + ((X) << 3))
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#define MPI_CYA_CFG 0x1000
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#define MPI_CLKEN 0x1080
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#define MPI_CFG_ENABLE BIT_ULL(0)
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#define MPI_CFG_IDLELO BIT_ULL(1)
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#define MPI_CFG_CLK_CONT BIT_ULL(2)
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#define MPI_CFG_WIREOR BIT_ULL(3)
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#define MPI_CFG_LSBFIRST BIT_ULL(4)
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#define MPI_CFG_CS_STICKY BIT_ULL(5)
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#define MPI_CFG_CSHI BIT_ULL(7)
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#define MPI_CFG_IDLECLKS GENMASK_ULL(9, 8)
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#define MPI_CFG_TRITX BIT_ULL(10)
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#define MPI_CFG_CSLATE BIT_ULL(11)
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#define MPI_CFG_CSENA0 BIT_ULL(12)
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#define MPI_CFG_CSENA1 BIT_ULL(13)
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#define MPI_CFG_CSENA2 BIT_ULL(14)
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#define MPI_CFG_CSENA3 BIT_ULL(15)
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#define MPI_CFG_CLKDIV GENMASK_ULL(28, 16)
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#define MPI_CFG_LEGACY_DIS BIT_ULL(31)
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#define MPI_CFG_IOMODE GENMASK_ULL(35, 34)
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#define MPI_CFG_TB100_EN BIT_ULL(49)
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#define MPI_DAT_DATA GENMASK_ULL(7, 0)
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#define MPI_STS_BUSY BIT_ULL(0)
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#define MPI_STS_MPI_INTR BIT_ULL(1)
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#define MPI_STS_RXNUM GENMASK_ULL(12, 8)
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#define MPI_TX_TOTNUM GENMASK_ULL(4, 0)
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#define MPI_TX_TXNUM GENMASK_ULL(12, 8)
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#define MPI_TX_LEAVECS BIT_ULL(16)
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#define MPI_TX_CSID GENMASK_ULL(21, 20)
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#define MPI_XMIT_TOTNUM GENMASK_ULL(10, 0)
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#define MPI_XMIT_TXNUM GENMASK_ULL(30, 20)
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#define MPI_XMIT_BUF_SEL BIT_ULL(59)
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#define MPI_XMIT_LEAVECS BIT_ULL(60)
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#define MPI_XMIT_CSID GENMASK_ULL(62, 61)
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/* Used on Octeon TX2 */
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void board_acquire_flash_arb(bool acquire);
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/* Local driver data structure */
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struct octeon_spi {
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void __iomem *base; /* Register base address */
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struct clk clk;
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u32 clkdiv; /* Clock divisor for device speed */
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};
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static u64 octeon_spi_set_mpicfg(struct udevice *dev)
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{
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struct dm_spi_slave_plat *slave = dev_get_parent_plat(dev);
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struct udevice *bus = dev_get_parent(dev);
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struct octeon_spi *priv = dev_get_priv(bus);
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u64 mpi_cfg;
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uint max_speed = slave->max_hz;
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bool cpha, cpol;
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if (!max_speed)
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max_speed = 12500000;
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if (max_speed > OCTEON_SPI_MAX_CLOCK_HZ)
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max_speed = OCTEON_SPI_MAX_CLOCK_HZ;
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debug("\n slave params %d %d %d\n", slave->cs,
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slave->max_hz, slave->mode);
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cpha = !!(slave->mode & SPI_CPHA);
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cpol = !!(slave->mode & SPI_CPOL);
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mpi_cfg = FIELD_PREP(MPI_CFG_CLKDIV, priv->clkdiv & 0x1fff) |
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FIELD_PREP(MPI_CFG_CSHI, !!(slave->mode & SPI_CS_HIGH)) |
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FIELD_PREP(MPI_CFG_LSBFIRST, !!(slave->mode & SPI_LSB_FIRST)) |
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FIELD_PREP(MPI_CFG_WIREOR, !!(slave->mode & SPI_3WIRE)) |
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FIELD_PREP(MPI_CFG_IDLELO, cpha != cpol) |
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FIELD_PREP(MPI_CFG_CSLATE, cpha) |
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MPI_CFG_CSENA0 | MPI_CFG_CSENA1 |
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MPI_CFG_CSENA2 | MPI_CFG_CSENA1 |
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MPI_CFG_ENABLE;
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debug("\n mpi_cfg %llx\n", mpi_cfg);
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return mpi_cfg;
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}
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/**
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* Wait until the SPI bus is ready
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*
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* @param dev SPI device to wait for
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*/
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static void octeon_spi_wait_ready(struct udevice *dev)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct octeon_spi *priv = dev_get_priv(bus);
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void *base = priv->base;
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u64 mpi_sts;
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do {
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mpi_sts = readq(base + MPI_STS);
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WATCHDOG_RESET();
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} while (mpi_sts & MPI_STS_BUSY);
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debug("%s(%s)\n", __func__, dev->name);
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}
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/**
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* Claim the bus for a slave device
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*
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* @param dev SPI bus
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*
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* @return 0 for success, -EINVAL if chip select is invalid
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*/
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static int octeon_spi_claim_bus(struct udevice *dev)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct octeon_spi *priv = dev_get_priv(bus);
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void *base = priv->base;
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u64 mpi_cfg;
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debug("\n\n%s(%s)\n", __func__, dev->name);
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if (!OCTEON_SPI_CS_VALID(spi_chip_select(dev)))
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return -EINVAL;
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if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2))
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board_acquire_flash_arb(true);
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mpi_cfg = readq(base + MPI_CFG);
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mpi_cfg &= ~MPI_CFG_TRITX;
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mpi_cfg |= MPI_CFG_ENABLE;
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writeq(mpi_cfg, base + MPI_CFG);
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mpi_cfg = readq(base + MPI_CFG);
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udelay(5); /** Wait for bus to settle */
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return 0;
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}
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/**
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* Release the bus to a slave device
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*
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* @param dev SPI bus
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*
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* @return 0 for success, -EINVAL if chip select is invalid
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*/
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static int octeon_spi_release_bus(struct udevice *dev)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct octeon_spi *priv = dev_get_priv(bus);
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void *base = priv->base;
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u64 mpi_cfg;
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debug("%s(%s)\n\n", __func__, dev->name);
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if (!OCTEON_SPI_CS_VALID(spi_chip_select(dev)))
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return -EINVAL;
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if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2))
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board_acquire_flash_arb(false);
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mpi_cfg = readq(base + MPI_CFG);
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mpi_cfg &= ~MPI_CFG_ENABLE;
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writeq(mpi_cfg, base + MPI_CFG);
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mpi_cfg = readq(base + MPI_CFG);
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udelay(1);
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return 0;
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}
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static int octeon_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct octeon_spi *priv = dev_get_priv(bus);
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void *base = priv->base;
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u64 mpi_tx;
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u64 mpi_cfg;
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u64 wide_dat = 0;
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int len = bitlen / 8;
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int i;
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const u8 *tx_data = dout;
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u8 *rx_data = din;
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int cs = spi_chip_select(dev);
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if (!OCTEON_SPI_CS_VALID(cs))
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return -EINVAL;
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debug("\n %s(%s, %u, %p, %p, 0x%lx), cs: %d\n",
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__func__, dev->name, bitlen, dout, din, flags, cs);
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mpi_cfg = octeon_spi_set_mpicfg(dev);
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if (mpi_cfg != readq(base + MPI_CFG)) {
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writeq(mpi_cfg, base + MPI_CFG);
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mpi_cfg = readq(base + MPI_CFG);
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udelay(10);
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}
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debug("\n mpi_cfg upd %llx\n", mpi_cfg);
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/*
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* Start by writing and reading 8 bytes at a time. While we can support
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* up to 10, it's easier to just use 8 with the MPI_WIDE_DAT register.
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*/
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while (len > 8) {
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if (tx_data) {
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wide_dat = get_unaligned((u64 *)tx_data);
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debug(" tx: %016llx \t", (unsigned long long)wide_dat);
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tx_data += 8;
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writeq(wide_dat, base + MPI_WIDE_DAT);
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}
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mpi_tx = FIELD_PREP(MPI_TX_CSID, cs) |
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FIELD_PREP(MPI_TX_LEAVECS, 1) |
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FIELD_PREP(MPI_TX_TXNUM, tx_data ? 8 : 0) |
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FIELD_PREP(MPI_TX_TOTNUM, 8);
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writeq(mpi_tx, base + MPI_TX);
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octeon_spi_wait_ready(dev);
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debug("\n ");
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if (rx_data) {
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wide_dat = readq(base + MPI_WIDE_DAT);
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debug(" rx: %016llx\t", (unsigned long long)wide_dat);
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*(u64 *)rx_data = wide_dat;
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rx_data += 8;
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}
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len -= 8;
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}
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debug("\n ");
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/* Write and read the rest of the data */
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if (tx_data) {
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for (i = 0; i < len; i++) {
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debug(" tx: %02x\n", *tx_data);
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writeq(*tx_data++, base + MPI_DAT(i));
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}
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}
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mpi_tx = FIELD_PREP(MPI_TX_CSID, cs) |
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FIELD_PREP(MPI_TX_LEAVECS, !(flags & SPI_XFER_END)) |
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FIELD_PREP(MPI_TX_TXNUM, tx_data ? len : 0) |
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FIELD_PREP(MPI_TX_TOTNUM, len);
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writeq(mpi_tx, base + MPI_TX);
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octeon_spi_wait_ready(dev);
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debug("\n ");
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if (rx_data) {
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for (i = 0; i < len; i++) {
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*rx_data = readq(base + MPI_DAT(i)) & 0xff;
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debug(" rx: %02x\n", *rx_data);
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rx_data++;
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}
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}
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return 0;
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}
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static int octeontx2_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct octeon_spi *priv = dev_get_priv(bus);
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void *base = priv->base;
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u64 mpi_xmit;
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u64 mpi_cfg;
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u64 wide_dat = 0;
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int len = bitlen / 8;
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int rem;
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int i;
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const u8 *tx_data = dout;
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u8 *rx_data = din;
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int cs = spi_chip_select(dev);
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if (!OCTEON_SPI_CS_VALID(cs))
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return -EINVAL;
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debug("\n %s(%s, %u, %p, %p, 0x%lx), cs: %d\n",
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__func__, dev->name, bitlen, dout, din, flags, cs);
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mpi_cfg = octeon_spi_set_mpicfg(dev);
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mpi_cfg |= MPI_CFG_TRITX | MPI_CFG_LEGACY_DIS | MPI_CFG_CS_STICKY |
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MPI_CFG_TB100_EN;
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mpi_cfg &= ~MPI_CFG_IOMODE;
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if (flags & (SPI_TX_DUAL | SPI_RX_DUAL))
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mpi_cfg |= FIELD_PREP(MPI_CFG_IOMODE, 2);
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if (flags & (SPI_TX_QUAD | SPI_RX_QUAD))
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mpi_cfg |= FIELD_PREP(MPI_CFG_IOMODE, 3);
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if (mpi_cfg != readq(base + MPI_CFG)) {
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writeq(mpi_cfg, base + MPI_CFG);
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mpi_cfg = readq(base + MPI_CFG);
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udelay(10);
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}
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debug("\n mpi_cfg upd %llx\n\n", mpi_cfg);
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/* Start by writing or reading 1024 bytes at a time. */
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while (len > 1024) {
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if (tx_data) {
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/* 8 bytes per iteration */
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for (i = 0; i < 128; i++) {
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wide_dat = get_unaligned((u64 *)tx_data);
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debug(" tx: %016llx \t",
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(unsigned long long)wide_dat);
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if ((i % 4) == 3)
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debug("\n");
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tx_data += 8;
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writeq(wide_dat, base + MPI_WIDE_BUF(i));
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}
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}
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mpi_xmit = FIELD_PREP(MPI_XMIT_CSID, cs) | MPI_XMIT_LEAVECS |
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FIELD_PREP(MPI_XMIT_TXNUM, tx_data ? 1024 : 0) |
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FIELD_PREP(MPI_XMIT_TOTNUM, 1024);
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writeq(mpi_xmit, base + MPI_XMIT);
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octeon_spi_wait_ready(dev);
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debug("\n ");
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if (rx_data) {
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/* 8 bytes per iteration */
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for (i = 0; i < 128; i++) {
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wide_dat = readq(base + MPI_WIDE_BUF(i));
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debug(" rx: %016llx\t",
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(unsigned long long)wide_dat);
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if ((i % 4) == 3)
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debug("\n");
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*(u64 *)rx_data = wide_dat;
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rx_data += 8;
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}
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}
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len -= 1024;
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}
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if (tx_data) {
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rem = len % 8;
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/* 8 bytes per iteration */
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for (i = 0; i < len / 8; i++) {
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wide_dat = get_unaligned((u64 *)tx_data);
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debug(" tx: %016llx \t",
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(unsigned long long)wide_dat);
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if ((i % 4) == 3)
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debug("\n");
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tx_data += 8;
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writeq(wide_dat, base + MPI_WIDE_BUF(i));
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}
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if (rem) {
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memcpy(&wide_dat, tx_data, rem);
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debug(" rtx: %016llx\t", wide_dat);
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writeq(wide_dat, base + MPI_WIDE_BUF(i));
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}
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}
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mpi_xmit = FIELD_PREP(MPI_XMIT_CSID, cs) |
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FIELD_PREP(MPI_XMIT_LEAVECS, !(flags & SPI_XFER_END)) |
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FIELD_PREP(MPI_XMIT_TXNUM, tx_data ? len : 0) |
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FIELD_PREP(MPI_XMIT_TOTNUM, len);
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writeq(mpi_xmit, base + MPI_XMIT);
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octeon_spi_wait_ready(dev);
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debug("\n ");
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if (rx_data) {
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rem = len % 8;
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/* 8 bytes per iteration */
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for (i = 0; i < len / 8; i++) {
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wide_dat = readq(base + MPI_WIDE_BUF(i));
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debug(" rx: %016llx\t",
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(unsigned long long)wide_dat);
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if ((i % 4) == 3)
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debug("\n");
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*(u64 *)rx_data = wide_dat;
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rx_data += 8;
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}
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if (rem) {
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wide_dat = readq(base + MPI_WIDE_BUF(i));
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debug(" rrx: %016llx\t",
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(unsigned long long)wide_dat);
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memcpy(rx_data, &wide_dat, rem);
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rx_data += rem;
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}
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}
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return 0;
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}
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static bool octeon_spi_supports_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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/* For now, support only below combinations
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* 1-1-1
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* 1-1-2 1-2-2
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* 1-1-4 1-4-4
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*/
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if (op->cmd.buswidth != 1)
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return false;
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return true;
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}
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static int octeon_spi_exec_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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unsigned long flags = SPI_XFER_BEGIN;
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const void *tx;
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void *rx;
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u8 opcode, *buf;
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u8 *addr;
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int i, temp, ret;
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if (op->cmd.buswidth != 1)
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return -ENOTSUPP;
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/* Send CMD */
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i = 0;
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opcode = op->cmd.opcode;
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if (!op->data.nbytes && !op->addr.nbytes && !op->dummy.nbytes)
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flags |= SPI_XFER_END;
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ret = octeontx2_spi_xfer(slave->dev, 8, (void *)&opcode, NULL, flags);
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if (ret < 0)
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return ret;
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/* Send Address and dummy */
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if (op->addr.nbytes) {
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/* Alloc buffer for address+dummy */
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buf = (u8 *)calloc(1, op->addr.nbytes + op->dummy.nbytes);
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if (!buf) {
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printf("%s Out of memory\n", __func__);
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return -ENOMEM;
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}
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addr = (u8 *)&op->addr.val;
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for (temp = 0; temp < op->addr.nbytes; temp++)
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buf[i++] = *(u8 *)(addr + op->addr.nbytes - 1 - temp);
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for (temp = 0; temp < op->dummy.nbytes; temp++)
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buf[i++] = 0xff;
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if (op->addr.buswidth == 2)
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flags |= SPI_RX_DUAL;
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|
if (op->addr.buswidth == 4)
|
|
flags |= SPI_RX_QUAD;
|
|
|
|
if (!op->data.nbytes)
|
|
flags |= SPI_XFER_END;
|
|
ret = octeontx2_spi_xfer(slave->dev, i * 8, (void *)buf, NULL,
|
|
flags);
|
|
free(buf);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
if (!op->data.nbytes)
|
|
return 0;
|
|
|
|
/* Send/Receive Data */
|
|
flags |= SPI_XFER_END;
|
|
if (op->data.buswidth == 2)
|
|
flags |= SPI_RX_DUAL;
|
|
if (op->data.buswidth == 4)
|
|
flags |= SPI_RX_QUAD;
|
|
|
|
rx = (op->data.dir == SPI_MEM_DATA_IN) ? op->data.buf.in : NULL;
|
|
tx = (op->data.dir == SPI_MEM_DATA_OUT) ? op->data.buf.out : NULL;
|
|
|
|
ret = octeontx2_spi_xfer(slave->dev, (op->data.nbytes * 8), tx, rx,
|
|
flags);
|
|
return ret;
|
|
}
|
|
|
|
static const struct spi_controller_mem_ops octeontx2_spi_mem_ops = {
|
|
.supports_op = octeon_spi_supports_op,
|
|
.exec_op = octeon_spi_exec_op,
|
|
};
|
|
|
|
/**
|
|
* Set the speed of the SPI bus
|
|
*
|
|
* @param bus bus to set
|
|
* @param max_hz maximum speed supported
|
|
*/
|
|
static int octeon_spi_set_speed(struct udevice *bus, uint max_hz)
|
|
{
|
|
struct octeon_spi *priv = dev_get_priv(bus);
|
|
ulong clk_rate;
|
|
u32 calc_hz;
|
|
|
|
if (max_hz > OCTEON_SPI_MAX_CLOCK_HZ)
|
|
max_hz = OCTEON_SPI_MAX_CLOCK_HZ;
|
|
|
|
if (device_is_compatible(bus, "cavium,thunderx-spi"))
|
|
clk_rate = 100000000;
|
|
else
|
|
clk_rate = clk_get_rate(&priv->clk);
|
|
if (IS_ERR_VALUE(clk_rate))
|
|
return -EINVAL;
|
|
|
|
debug("%s(%s, %u, %lu)\n", __func__, bus->name, max_hz, clk_rate);
|
|
|
|
priv->clkdiv = clk_rate / (2 * max_hz);
|
|
while (1) {
|
|
calc_hz = clk_rate / (2 * priv->clkdiv);
|
|
if (calc_hz <= max_hz)
|
|
break;
|
|
priv->clkdiv += 1;
|
|
}
|
|
|
|
if (priv->clkdiv > 8191)
|
|
return -EINVAL;
|
|
|
|
debug("%s: clkdiv=%d\n", __func__, priv->clkdiv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int octeon_spi_set_mode(struct udevice *bus, uint mode)
|
|
{
|
|
/* We don't set it here */
|
|
return 0;
|
|
}
|
|
|
|
static struct dm_spi_ops octeon_spi_ops = {
|
|
.claim_bus = octeon_spi_claim_bus,
|
|
.release_bus = octeon_spi_release_bus,
|
|
.set_speed = octeon_spi_set_speed,
|
|
.set_mode = octeon_spi_set_mode,
|
|
.xfer = octeon_spi_xfer,
|
|
};
|
|
|
|
static int octeon_spi_probe(struct udevice *dev)
|
|
{
|
|
struct octeon_spi *priv = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
/* Octeon TX & TX2 use PCI based probing */
|
|
if (device_is_compatible(dev, "cavium,thunder-8190-spi")) {
|
|
pci_dev_t bdf = dm_pci_get_bdf(dev);
|
|
|
|
debug("SPI PCI device: %x\n", bdf);
|
|
priv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0,
|
|
PCI_REGION_MEM);
|
|
/* Add base offset */
|
|
priv->base += 0x1000;
|
|
|
|
/*
|
|
* Octeon TX2 needs a different xfer function and supports
|
|
* mem_ops
|
|
*/
|
|
if (device_is_compatible(dev, "cavium,thunderx-spi")) {
|
|
octeon_spi_ops.xfer = octeontx2_spi_xfer;
|
|
octeon_spi_ops.mem_ops = &octeontx2_spi_mem_ops;
|
|
}
|
|
} else {
|
|
priv->base = dev_remap_addr(dev);
|
|
}
|
|
|
|
ret = clk_get_by_index(dev, 0, &priv->clk);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = clk_enable(&priv->clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
debug("SPI bus %s %d at %p\n", dev->name, dev_seq(dev), priv->base);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id octeon_spi_ids[] = {
|
|
/* MIPS Octeon */
|
|
{ .compatible = "cavium,octeon-3010-spi" },
|
|
/* ARM Octeon TX / TX2 */
|
|
{ .compatible = "cavium,thunder-8190-spi" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(octeon_spi) = {
|
|
.name = "spi_octeon",
|
|
.id = UCLASS_SPI,
|
|
.of_match = octeon_spi_ids,
|
|
.probe = octeon_spi_probe,
|
|
.priv_auto = sizeof(struct octeon_spi),
|
|
.ops = &octeon_spi_ops,
|
|
};
|