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![Simon Glass](/assets/img/avatar_default.png)
With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
1004 lines
26 KiB
C
1004 lines
26 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2011-12 The Chromium OS Authors.
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*
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* This file is derived from the flashrom project.
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*/
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#define LOG_CATEGORY UCLASS_SPI
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#include <common.h>
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#include <bootstage.h>
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#include <div64.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <errno.h>
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#include <log.h>
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#include <malloc.h>
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#include <pch.h>
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#include <pci.h>
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#include <pci_ids.h>
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#include <spi.h>
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#include <spi_flash.h>
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#include <spi-mem.h>
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#include <spl.h>
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#include <asm/fast_spi.h>
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#include <asm/io.h>
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#include <dm/uclass-internal.h>
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#include <asm/mtrr.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/sizes.h>
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#include "ich.h"
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#ifdef DEBUG_TRACE
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#define debug_trace(fmt, args...) debug(fmt, ##args)
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#else
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#define debug_trace(x, args...)
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#endif
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static u8 ich_readb(struct ich_spi_priv *priv, int reg)
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{
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u8 value = readb(priv->base + reg);
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debug_trace("read %2.2x from %4.4x\n", value, reg);
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return value;
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}
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static u16 ich_readw(struct ich_spi_priv *priv, int reg)
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{
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u16 value = readw(priv->base + reg);
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debug_trace("read %4.4x from %4.4x\n", value, reg);
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return value;
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}
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static u32 ich_readl(struct ich_spi_priv *priv, int reg)
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{
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u32 value = readl(priv->base + reg);
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debug_trace("read %8.8x from %4.4x\n", value, reg);
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return value;
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}
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static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg)
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{
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writeb(value, priv->base + reg);
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debug_trace("wrote %2.2x to %4.4x\n", value, reg);
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}
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static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg)
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{
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writew(value, priv->base + reg);
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debug_trace("wrote %4.4x to %4.4x\n", value, reg);
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}
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static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg)
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{
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writel(value, priv->base + reg);
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debug_trace("wrote %8.8x to %4.4x\n", value, reg);
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}
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static void write_reg(struct ich_spi_priv *priv, const void *value,
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int dest_reg, uint32_t size)
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{
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memcpy_toio(priv->base + dest_reg, value, size);
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}
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static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value,
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uint32_t size)
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{
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memcpy_fromio(value, priv->base + src_reg, size);
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}
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static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
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{
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const uint32_t bbar_mask = 0x00ffff00;
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uint32_t ichspi_bbar;
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if (ctlr->bbar) {
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minaddr &= bbar_mask;
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ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
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ichspi_bbar |= minaddr;
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ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
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}
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}
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/* @return 1 if the SPI flash supports the 33MHz speed */
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static bool ich9_can_do_33mhz(struct udevice *dev)
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{
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struct ich_spi_priv *priv = dev_get_priv(dev);
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u32 fdod, speed;
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if (!CONFIG_IS_ENABLED(PCI))
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return false;
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/* Observe SPI Descriptor Component Section 0 */
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dm_pci_write_config32(priv->pch, 0xb0, 0x1000);
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/* Extract the Write/Erase SPI Frequency from descriptor */
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dm_pci_read_config32(priv->pch, 0xb4, &fdod);
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/* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
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speed = (fdod >> 21) & 7;
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return speed == 1;
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}
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static void spi_lock_down(struct ich_spi_plat *plat, void *sbase)
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{
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if (plat->ich_version == ICHV_7) {
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struct ich7_spi_regs *ich7_spi = sbase;
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setbits_le16(&ich7_spi->spis, SPIS_LOCK);
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} else if (plat->ich_version == ICHV_9) {
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struct ich9_spi_regs *ich9_spi = sbase;
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setbits_le16(&ich9_spi->hsfs, HSFS_FLOCKDN);
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}
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}
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static bool spi_lock_status(struct ich_spi_plat *plat, void *sbase)
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{
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int lock = 0;
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if (plat->ich_version == ICHV_7) {
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struct ich7_spi_regs *ich7_spi = sbase;
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lock = readw(&ich7_spi->spis) & SPIS_LOCK;
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} else if (plat->ich_version == ICHV_9) {
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struct ich9_spi_regs *ich9_spi = sbase;
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lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
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}
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return lock != 0;
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}
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static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans,
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bool lock)
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{
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uint16_t optypes;
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uint8_t opmenu[ctlr->menubytes];
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if (!lock) {
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/* The lock is off, so just use index 0. */
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ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
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optypes = ich_readw(ctlr, ctlr->optype);
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optypes = (optypes & 0xfffc) | (trans->type & 0x3);
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ich_writew(ctlr, optypes, ctlr->optype);
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return 0;
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} else {
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/* The lock is on. See if what we need is on the menu. */
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uint8_t optype;
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uint16_t opcode_index;
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/* Write Enable is handled as atomic prefix */
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if (trans->opcode == SPI_OPCODE_WREN)
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return 0;
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read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu));
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for (opcode_index = 0; opcode_index < ctlr->menubytes;
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opcode_index++) {
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if (opmenu[opcode_index] == trans->opcode)
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break;
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}
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if (opcode_index == ctlr->menubytes) {
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debug("ICH SPI: Opcode %x not found\n", trans->opcode);
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return -EINVAL;
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}
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optypes = ich_readw(ctlr, ctlr->optype);
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optype = (optypes >> (opcode_index * 2)) & 0x3;
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if (optype != trans->type) {
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debug("ICH SPI: Transaction doesn't fit type %d\n",
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optype);
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return -ENOSPC;
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}
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return opcode_index;
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}
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}
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/*
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* Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
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* below is true) or 0. In case the wait was for the bit(s) to set - write
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* those bits back, which would cause resetting them.
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*
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* Return the last read status value on success or -1 on failure.
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*/
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static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask,
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int wait_til_set)
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{
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int timeout = 600000; /* This will result in 6s */
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u16 status = 0;
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while (timeout--) {
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status = ich_readw(ctlr, ctlr->status);
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if (wait_til_set ^ ((status & bitmask) == 0)) {
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if (wait_til_set) {
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ich_writew(ctlr, status & bitmask,
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ctlr->status);
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}
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return status;
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}
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udelay(10);
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}
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debug("ICH SPI: SCIP timeout, read %x, expected %x, wts %x %x\n",
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status, bitmask, wait_til_set, status & bitmask);
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return -ETIMEDOUT;
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}
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static void ich_spi_config_opcode(struct udevice *dev)
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{
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struct ich_spi_priv *ctlr = dev_get_priv(dev);
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/*
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* PREOP, OPTYPE, OPMENU1/OPMENU2 registers can be locked down
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* to prevent accidental or intentional writes. Before they get
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* locked down, these registers should be initialized properly.
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*/
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ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop);
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ich_writew(ctlr, SPI_OPTYPE, ctlr->optype);
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ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu);
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ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
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}
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static int ich_spi_exec_op_swseq(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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struct udevice *bus = dev_get_parent(slave->dev);
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struct ich_spi_plat *plat = dev_get_plat(bus);
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struct ich_spi_priv *ctlr = dev_get_priv(bus);
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uint16_t control;
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int16_t opcode_index;
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int with_address;
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int status;
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struct spi_trans *trans = &ctlr->trans;
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bool lock = spi_lock_status(plat, ctlr->base);
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int ret = 0;
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trans->in = NULL;
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trans->out = NULL;
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trans->type = 0xFF;
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if (op->data.nbytes) {
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if (op->data.dir == SPI_MEM_DATA_IN) {
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trans->in = op->data.buf.in;
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trans->bytesin = op->data.nbytes;
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} else {
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trans->out = op->data.buf.out;
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trans->bytesout = op->data.nbytes;
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}
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}
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if (trans->opcode != op->cmd.opcode)
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trans->opcode = op->cmd.opcode;
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if (lock && trans->opcode == SPI_OPCODE_WRDIS)
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return 0;
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if (trans->opcode == SPI_OPCODE_WREN) {
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/*
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* Treat Write Enable as Atomic Pre-Op if possible
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* in order to prevent the Management Engine from
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* issuing a transaction between WREN and DATA.
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*/
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if (!lock)
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ich_writew(ctlr, trans->opcode, ctlr->preop);
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return 0;
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}
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ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
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if (ret < 0)
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return ret;
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if (plat->ich_version == ICHV_7)
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ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
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else
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ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
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/* Try to guess spi transaction type */
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if (op->data.dir == SPI_MEM_DATA_OUT) {
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if (op->addr.nbytes)
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trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
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else
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trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
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} else {
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if (op->addr.nbytes)
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trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
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else
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trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
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}
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/* Special erase case handling */
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if (op->addr.nbytes && !op->data.buswidth)
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trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
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opcode_index = spi_setup_opcode(ctlr, trans, lock);
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if (opcode_index < 0)
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return -EINVAL;
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if (op->addr.nbytes) {
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trans->offset = op->addr.val;
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with_address = 1;
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}
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if (ctlr->speed && ctlr->max_speed >= 33000000) {
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int byte;
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byte = ich_readb(ctlr, ctlr->speed);
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if (ctlr->cur_speed >= 33000000)
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byte |= SSFC_SCF_33MHZ;
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else
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byte &= ~SSFC_SCF_33MHZ;
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ich_writeb(ctlr, byte, ctlr->speed);
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}
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/* Preset control fields */
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control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
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/* Issue atomic preop cycle if needed */
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if (ich_readw(ctlr, ctlr->preop))
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control |= SPIC_ACS;
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if (!trans->bytesout && !trans->bytesin) {
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/* SPI addresses are 24 bit only */
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if (with_address) {
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ich_writel(ctlr, trans->offset & 0x00FFFFFF,
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ctlr->addr);
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}
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/*
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* This is a 'no data' command (like Write Enable), its
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* bitesout size was 1, decremented to zero while executing
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* spi_setup_opcode() above. Tell the chip to send the
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* command.
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*/
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ich_writew(ctlr, control, ctlr->control);
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/* wait for the result */
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status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
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if (status < 0)
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return status;
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if (status & SPIS_FCERR) {
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debug("ICH SPI: Command transaction error\n");
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return -EIO;
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}
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return 0;
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}
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while (trans->bytesout || trans->bytesin) {
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uint32_t data_length;
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/* SPI addresses are 24 bit only */
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ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr);
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if (trans->bytesout)
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data_length = min(trans->bytesout, ctlr->databytes);
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else
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data_length = min(trans->bytesin, ctlr->databytes);
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/* Program data into FDATA0 to N */
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if (trans->bytesout) {
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write_reg(ctlr, trans->out, ctlr->data, data_length);
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trans->bytesout -= data_length;
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}
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/* Add proper control fields' values */
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control &= ~((ctlr->databytes - 1) << 8);
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control |= SPIC_DS;
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control |= (data_length - 1) << 8;
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/* write it */
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ich_writew(ctlr, control, ctlr->control);
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/* Wait for Cycle Done Status or Flash Cycle Error */
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status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
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if (status < 0)
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return status;
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if (status & SPIS_FCERR) {
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debug("ICH SPI: Data transaction error %x\n", status);
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return -EIO;
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}
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if (trans->bytesin) {
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read_reg(ctlr, ctlr->data, trans->in, data_length);
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trans->bytesin -= data_length;
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}
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}
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/* Clear atomic preop now that xfer is done */
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if (!lock)
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ich_writew(ctlr, 0, ctlr->preop);
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return 0;
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}
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/*
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* Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and
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* that the operation does not cross page boundary.
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*/
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static uint get_xfer_len(u32 offset, int len, int page_size)
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{
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uint xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE);
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uint bytes_left = ALIGN(offset, page_size) - offset;
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if (bytes_left)
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xfer_len = min(xfer_len, bytes_left);
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return xfer_len;
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}
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/* Fill FDATAn FIFO in preparation for a write transaction */
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static void fill_xfer_fifo(struct fast_spi_regs *regs, const void *data,
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uint len)
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{
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memcpy(regs->fdata, data, len);
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}
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/* Drain FDATAn FIFO after a read transaction populates data */
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static void drain_xfer_fifo(struct fast_spi_regs *regs, void *dest, uint len)
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{
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memcpy(dest, regs->fdata, len);
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}
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/* Fire up a transfer using the hardware sequencer */
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static void start_hwseq_xfer(struct fast_spi_regs *regs, uint hsfsts_cycle,
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uint offset, uint len)
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{
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/* Make sure all W1C status bits get cleared */
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u32 hsfsts;
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hsfsts = readl(®s->hsfsts_ctl);
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hsfsts &= ~(HSFSTS_FCYCLE_MASK | HSFSTS_FDBC_MASK);
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hsfsts |= HSFSTS_AEL | HSFSTS_FCERR | HSFSTS_FDONE;
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/* Set up transaction parameters */
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hsfsts |= hsfsts_cycle << HSFSTS_FCYCLE_SHIFT;
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hsfsts |= ((len - 1) << HSFSTS_FDBC_SHIFT) & HSFSTS_FDBC_MASK;
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hsfsts |= HSFSTS_FGO;
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writel(offset, ®s->faddr);
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writel(hsfsts, ®s->hsfsts_ctl);
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}
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static int wait_for_hwseq_xfer(struct fast_spi_regs *regs, uint offset)
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{
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ulong start;
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u32 hsfsts;
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start = get_timer(0);
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do {
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hsfsts = readl(®s->hsfsts_ctl);
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if (hsfsts & HSFSTS_FCERR) {
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debug("SPI transaction error at offset %x HSFSTS = %08x\n",
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offset, hsfsts);
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return -EIO;
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}
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if (hsfsts & HSFSTS_AEL)
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return -EPERM;
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if (hsfsts & HSFSTS_FDONE)
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return 0;
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} while (get_timer(start) < SPIBAR_HWSEQ_XFER_TIMEOUT_MS);
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debug("SPI transaction timeout at offset %x HSFSTS = %08x, timer %d\n",
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offset, hsfsts, (uint)get_timer(start));
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return -ETIMEDOUT;
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}
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/**
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* exec_sync_hwseq_xfer() - Execute flash transfer by hardware sequencing
|
|
*
|
|
* This waits until complete or timeout
|
|
*
|
|
* @regs: SPI registers
|
|
* @hsfsts_cycle: Cycle type (enum hsfsts_cycle_t)
|
|
* @offset: Offset to access
|
|
* @len: Number of bytes to transfer (can be 0)
|
|
* @return 0 if OK, -EIO on flash-cycle error (FCERR), -EPERM on access error
|
|
* (AEL), -ETIMEDOUT on timeout
|
|
*/
|
|
static int exec_sync_hwseq_xfer(struct fast_spi_regs *regs, uint hsfsts_cycle,
|
|
uint offset, uint len)
|
|
{
|
|
start_hwseq_xfer(regs, hsfsts_cycle, offset, len);
|
|
|
|
return wait_for_hwseq_xfer(regs, offset);
|
|
}
|
|
|
|
static int ich_spi_exec_op_hwseq(struct spi_slave *slave,
|
|
const struct spi_mem_op *op)
|
|
{
|
|
struct spi_flash *flash = dev_get_uclass_priv(slave->dev);
|
|
struct udevice *bus = dev_get_parent(slave->dev);
|
|
struct ich_spi_priv *priv = dev_get_priv(bus);
|
|
struct fast_spi_regs *regs = priv->base;
|
|
uint page_size;
|
|
uint offset;
|
|
int cycle;
|
|
uint len;
|
|
bool out;
|
|
int ret;
|
|
u8 *buf;
|
|
|
|
offset = op->addr.val;
|
|
len = op->data.nbytes;
|
|
|
|
switch (op->cmd.opcode) {
|
|
case SPINOR_OP_RDID:
|
|
cycle = HSFSTS_CYCLE_RDID;
|
|
break;
|
|
case SPINOR_OP_READ_FAST:
|
|
cycle = HSFSTS_CYCLE_READ;
|
|
break;
|
|
case SPINOR_OP_PP:
|
|
cycle = HSFSTS_CYCLE_WRITE;
|
|
break;
|
|
case SPINOR_OP_WREN:
|
|
/* Nothing needs to be done */
|
|
return 0;
|
|
case SPINOR_OP_WRSR:
|
|
cycle = HSFSTS_CYCLE_WR_STATUS;
|
|
break;
|
|
case SPINOR_OP_RDSR:
|
|
cycle = HSFSTS_CYCLE_RD_STATUS;
|
|
break;
|
|
case SPINOR_OP_WRDI:
|
|
return 0; /* ignore */
|
|
case SPINOR_OP_BE_4K:
|
|
cycle = HSFSTS_CYCLE_4K_ERASE;
|
|
ret = exec_sync_hwseq_xfer(regs, cycle, offset, 0);
|
|
return ret;
|
|
default:
|
|
debug("Unknown cycle %x\n", op->cmd.opcode);
|
|
return -EINVAL;
|
|
};
|
|
|
|
out = op->data.dir == SPI_MEM_DATA_OUT;
|
|
buf = out ? (u8 *)op->data.buf.out : op->data.buf.in;
|
|
page_size = flash->page_size ? : 256;
|
|
|
|
while (len) {
|
|
uint xfer_len = get_xfer_len(offset, len, page_size);
|
|
|
|
if (out)
|
|
fill_xfer_fifo(regs, buf, xfer_len);
|
|
|
|
ret = exec_sync_hwseq_xfer(regs, cycle, offset, xfer_len);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (!out)
|
|
drain_xfer_fifo(regs, buf, xfer_len);
|
|
|
|
offset += xfer_len;
|
|
buf += xfer_len;
|
|
len -= xfer_len;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
|
|
{
|
|
struct udevice *bus = dev_get_parent(slave->dev);
|
|
struct ich_spi_plat *plat = dev_get_plat(bus);
|
|
int ret;
|
|
|
|
bootstage_start(BOOTSTAGE_ID_ACCUM_SPI, "fast_spi");
|
|
if (plat->hwseq)
|
|
ret = ich_spi_exec_op_hwseq(slave, op);
|
|
else
|
|
ret = ich_spi_exec_op_swseq(slave, op);
|
|
bootstage_accum(BOOTSTAGE_ID_ACCUM_SPI);
|
|
|
|
return ret;
|
|
}
|
|
|
|
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
/**
|
|
* ich_spi_get_basics() - Get basic information about the ICH device
|
|
*
|
|
* This works without probing any devices if requested.
|
|
*
|
|
* @bus: SPI controller to use
|
|
* @can_probe: true if this function is allowed to probe the PCH
|
|
* @pchp: Returns a pointer to the pch, or NULL if not found
|
|
* @ich_versionp: Returns ICH version detected on success
|
|
* @mmio_basep: Returns the address of the SPI registers on success
|
|
* @return 0 if OK, -EPROTOTYPE if the PCH could not be found, -EAGAIN if
|
|
* the function cannot success without probing, possible another error if
|
|
* pch_get_spi_base() fails
|
|
*/
|
|
static int ich_spi_get_basics(struct udevice *bus, bool can_probe,
|
|
struct udevice **pchp,
|
|
enum ich_version *ich_versionp, ulong *mmio_basep)
|
|
{
|
|
struct udevice *pch = NULL;
|
|
int ret = 0;
|
|
|
|
/* Find a PCH if there is one */
|
|
if (can_probe) {
|
|
pch = dev_get_parent(bus);
|
|
if (device_get_uclass_id(pch) != UCLASS_PCH) {
|
|
uclass_first_device(UCLASS_PCH, &pch);
|
|
if (!pch)
|
|
return log_msg_ret("uclass", -EPROTOTYPE);
|
|
}
|
|
}
|
|
|
|
*ich_versionp = dev_get_driver_data(bus);
|
|
if (*ich_versionp == ICHV_APL)
|
|
*mmio_basep = dm_pci_read_bar32(bus, 0);
|
|
else if (pch)
|
|
ret = pch_get_spi_base(pch, mmio_basep);
|
|
else
|
|
return -EAGAIN;
|
|
*pchp = pch;
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
/**
|
|
* ich_get_mmap_bus() - Handle the get_mmap() method for a bus
|
|
*
|
|
* There are several cases to consider:
|
|
* 1. Using of-platdata, in which case we have the BDF and can access the
|
|
* registers by reading the BAR
|
|
* 2. Not using of-platdata, but still with a SPI controller that is on its own
|
|
* PCI PDF. In this case we read the BDF from the parent plat and again get
|
|
* the registers by reading the BAR
|
|
* 3. Using a SPI controller that is a child of the PCH, in which case we try
|
|
* to find the registers by asking the PCH. This only works if the PCH has
|
|
* been probed (which it will be if the bus is probed since parents are
|
|
* probed before children), since the PCH may not have a PCI address until
|
|
* its parent (the PCI bus itself) has been probed. If you are using this
|
|
* method then you should make sure the SPI bus is probed.
|
|
*
|
|
* The first two cases are useful in early init. The last one is more useful
|
|
* afterwards.
|
|
*/
|
|
static int ich_get_mmap_bus(struct udevice *bus, ulong *map_basep,
|
|
uint *map_sizep, uint *offsetp)
|
|
{
|
|
pci_dev_t spi_bdf;
|
|
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
if (device_is_on_pci_bus(bus)) {
|
|
struct pci_child_plat *pplat;
|
|
|
|
pplat = dev_get_parent_plat(bus);
|
|
spi_bdf = pplat->devfn;
|
|
} else {
|
|
enum ich_version ich_version;
|
|
struct fast_spi_regs *regs;
|
|
struct udevice *pch;
|
|
ulong mmio_base;
|
|
int ret;
|
|
|
|
ret = ich_spi_get_basics(bus, device_active(bus), &pch,
|
|
&ich_version, &mmio_base);
|
|
if (ret)
|
|
return log_msg_ret("basics", ret);
|
|
regs = (struct fast_spi_regs *)mmio_base;
|
|
|
|
return fast_spi_get_bios_mmap_regs(regs, map_basep, map_sizep,
|
|
offsetp);
|
|
}
|
|
#else
|
|
struct ich_spi_plat *plat = dev_get_plat(bus);
|
|
|
|
/*
|
|
* We cannot rely on plat->bdf being set up yet since this method can
|
|
* be called before the device is probed. Use the of-platdata directly
|
|
* instead.
|
|
*/
|
|
spi_bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
|
|
#endif
|
|
|
|
return fast_spi_get_bios_mmap(spi_bdf, map_basep, map_sizep, offsetp);
|
|
}
|
|
|
|
static int ich_get_mmap(struct udevice *dev, ulong *map_basep, uint *map_sizep,
|
|
uint *offsetp)
|
|
{
|
|
struct udevice *bus = dev_get_parent(dev);
|
|
|
|
return ich_get_mmap_bus(bus, map_basep, map_sizep, offsetp);
|
|
}
|
|
|
|
static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op)
|
|
{
|
|
unsigned int page_offset;
|
|
int addr = op->addr.val;
|
|
unsigned int byte_count = op->data.nbytes;
|
|
|
|
if (hweight32(ICH_BOUNDARY) == 1) {
|
|
page_offset = addr & (ICH_BOUNDARY - 1);
|
|
} else {
|
|
u64 aux = addr;
|
|
|
|
page_offset = do_div(aux, ICH_BOUNDARY);
|
|
}
|
|
|
|
if (op->data.dir == SPI_MEM_DATA_IN) {
|
|
if (slave->max_read_size) {
|
|
op->data.nbytes = min(ICH_BOUNDARY - page_offset,
|
|
slave->max_read_size);
|
|
}
|
|
} else if (slave->max_write_size) {
|
|
op->data.nbytes = min(ICH_BOUNDARY - page_offset,
|
|
slave->max_write_size);
|
|
}
|
|
|
|
op->data.nbytes = min(op->data.nbytes, byte_count);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ich_protect_lockdown(struct udevice *dev)
|
|
{
|
|
struct ich_spi_plat *plat = dev_get_plat(dev);
|
|
struct ich_spi_priv *priv = dev_get_priv(dev);
|
|
int ret = -ENOSYS;
|
|
|
|
/* Disable the BIOS write protect so write commands are allowed */
|
|
if (priv->pch)
|
|
ret = pch_set_spi_protect(priv->pch, false);
|
|
if (ret == -ENOSYS) {
|
|
u8 bios_cntl;
|
|
|
|
bios_cntl = ich_readb(priv, priv->bcr);
|
|
bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */
|
|
bios_cntl |= 1; /* Write Protect Disable (WPD) */
|
|
ich_writeb(priv, bios_cntl, priv->bcr);
|
|
} else if (ret) {
|
|
debug("%s: Failed to disable write-protect: err=%d\n",
|
|
__func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
/* Lock down SPI controller settings if required */
|
|
if (plat->lockdown) {
|
|
ich_spi_config_opcode(dev);
|
|
spi_lock_down(plat, priv->base);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ich_init_controller(struct udevice *dev,
|
|
struct ich_spi_plat *plat,
|
|
struct ich_spi_priv *ctlr)
|
|
{
|
|
if (spl_phase() == PHASE_TPL) {
|
|
struct ich_spi_plat *plat = dev_get_plat(dev);
|
|
int ret;
|
|
|
|
ret = fast_spi_early_init(plat->bdf, plat->mmio_base);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
ctlr->base = (void *)plat->mmio_base;
|
|
if (plat->ich_version == ICHV_7) {
|
|
struct ich7_spi_regs *ich7_spi = ctlr->base;
|
|
|
|
ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
|
|
ctlr->menubytes = sizeof(ich7_spi->opmenu);
|
|
ctlr->optype = offsetof(struct ich7_spi_regs, optype);
|
|
ctlr->addr = offsetof(struct ich7_spi_regs, spia);
|
|
ctlr->data = offsetof(struct ich7_spi_regs, spid);
|
|
ctlr->databytes = sizeof(ich7_spi->spid);
|
|
ctlr->status = offsetof(struct ich7_spi_regs, spis);
|
|
ctlr->control = offsetof(struct ich7_spi_regs, spic);
|
|
ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
|
|
ctlr->preop = offsetof(struct ich7_spi_regs, preop);
|
|
} else if (plat->ich_version == ICHV_9) {
|
|
struct ich9_spi_regs *ich9_spi = ctlr->base;
|
|
|
|
ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
|
|
ctlr->menubytes = sizeof(ich9_spi->opmenu);
|
|
ctlr->optype = offsetof(struct ich9_spi_regs, optype);
|
|
ctlr->addr = offsetof(struct ich9_spi_regs, faddr);
|
|
ctlr->data = offsetof(struct ich9_spi_regs, fdata);
|
|
ctlr->databytes = sizeof(ich9_spi->fdata);
|
|
ctlr->status = offsetof(struct ich9_spi_regs, ssfs);
|
|
ctlr->control = offsetof(struct ich9_spi_regs, ssfc);
|
|
ctlr->speed = ctlr->control + 2;
|
|
ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
|
|
ctlr->preop = offsetof(struct ich9_spi_regs, preop);
|
|
ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
|
|
ctlr->pr = &ich9_spi->pr[0];
|
|
} else if (plat->ich_version == ICHV_APL) {
|
|
} else {
|
|
debug("ICH SPI: Unrecognised ICH version %d\n",
|
|
plat->ich_version);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Work out the maximum speed we can support */
|
|
ctlr->max_speed = 20000000;
|
|
if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev))
|
|
ctlr->max_speed = 33000000;
|
|
debug("ICH SPI: Version ID %d detected at %lx, speed %ld\n",
|
|
plat->ich_version, plat->mmio_base, ctlr->max_speed);
|
|
|
|
ich_set_bbar(ctlr, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ich_cache_bios_region(struct udevice *dev)
|
|
{
|
|
ulong map_base;
|
|
uint map_size;
|
|
uint offset;
|
|
ulong base;
|
|
int ret;
|
|
|
|
ret = ich_get_mmap_bus(dev, &map_base, &map_size, &offset);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Don't use WRBACK since we are not supposed to write to SPI flash */
|
|
base = SZ_4G - map_size;
|
|
mtrr_set_next_var(MTRR_TYPE_WRPROT, base, map_size);
|
|
log_debug("BIOS cache base=%lx, size=%x\n", base, (uint)map_size);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ich_spi_probe(struct udevice *dev)
|
|
{
|
|
struct ich_spi_plat *plat = dev_get_plat(dev);
|
|
struct ich_spi_priv *priv = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
ret = ich_init_controller(dev, plat, priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (spl_phase() == PHASE_TPL) {
|
|
/* Cache the BIOS to speed things up */
|
|
ret = ich_cache_bios_region(dev);
|
|
if (ret)
|
|
return ret;
|
|
} else {
|
|
ret = ich_protect_lockdown(dev);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
priv->cur_speed = priv->max_speed;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ich_spi_remove(struct udevice *bus)
|
|
{
|
|
/*
|
|
* Configure SPI controller so that the Linux MTD driver can fully
|
|
* access the SPI NOR chip
|
|
*/
|
|
ich_spi_config_opcode(bus);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ich_spi_set_speed(struct udevice *bus, uint speed)
|
|
{
|
|
struct ich_spi_priv *priv = dev_get_priv(bus);
|
|
|
|
priv->cur_speed = speed;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ich_spi_set_mode(struct udevice *bus, uint mode)
|
|
{
|
|
debug("%s: mode=%d\n", __func__, mode);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ich_spi_child_pre_probe(struct udevice *dev)
|
|
{
|
|
struct udevice *bus = dev_get_parent(dev);
|
|
struct ich_spi_plat *plat = dev_get_plat(bus);
|
|
struct ich_spi_priv *priv = dev_get_priv(bus);
|
|
struct spi_slave *slave = dev_get_parent_priv(dev);
|
|
|
|
/*
|
|
* Yes this controller can only write a small number of bytes at
|
|
* once! The limit is typically 64 bytes. For hardware sequencing a
|
|
* a loop is used to get around this.
|
|
*/
|
|
if (!plat->hwseq)
|
|
slave->max_write_size = priv->databytes;
|
|
/*
|
|
* ICH 7 SPI controller only supports array read command
|
|
* and byte program command for SST flash
|
|
*/
|
|
if (plat->ich_version == ICHV_7)
|
|
slave->mode = SPI_RX_SLOW | SPI_TX_BYTE;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ich_spi_of_to_plat(struct udevice *dev)
|
|
{
|
|
struct ich_spi_plat *plat = dev_get_plat(dev);
|
|
|
|
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
struct ich_spi_priv *priv = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
ret = ich_spi_get_basics(dev, true, &priv->pch, &plat->ich_version,
|
|
&plat->mmio_base);
|
|
if (ret)
|
|
return log_msg_ret("basics", ret);
|
|
plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down");
|
|
/*
|
|
* Use an int so that the property is present in of-platdata even
|
|
* when false.
|
|
*/
|
|
plat->hwseq = dev_read_u32_default(dev, "intel,hardware-seq", 0);
|
|
#else
|
|
plat->ich_version = ICHV_APL;
|
|
plat->mmio_base = plat->dtplat.early_regs[0];
|
|
plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
|
|
plat->hwseq = plat->dtplat.intel_hardware_seq;
|
|
#endif
|
|
debug("%s: mmio_base=%lx\n", __func__, plat->mmio_base);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct spi_controller_mem_ops ich_controller_mem_ops = {
|
|
.adjust_op_size = ich_spi_adjust_size,
|
|
.supports_op = NULL,
|
|
.exec_op = ich_spi_exec_op,
|
|
};
|
|
|
|
static const struct dm_spi_ops ich_spi_ops = {
|
|
/* xfer is not supported */
|
|
.set_speed = ich_spi_set_speed,
|
|
.set_mode = ich_spi_set_mode,
|
|
.mem_ops = &ich_controller_mem_ops,
|
|
.get_mmap = ich_get_mmap,
|
|
/*
|
|
* cs_info is not needed, since we require all chip selects to be
|
|
* in the device tree explicitly
|
|
*/
|
|
};
|
|
|
|
static const struct udevice_id ich_spi_ids[] = {
|
|
{ .compatible = "intel,ich7-spi", ICHV_7 },
|
|
{ .compatible = "intel,ich9-spi", ICHV_9 },
|
|
{ .compatible = "intel,fast-spi", ICHV_APL },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(intel_fast_spi) = {
|
|
.name = "intel_fast_spi",
|
|
.id = UCLASS_SPI,
|
|
.of_match = ich_spi_ids,
|
|
.ops = &ich_spi_ops,
|
|
.of_to_plat = ich_spi_of_to_plat,
|
|
.plat_auto = sizeof(struct ich_spi_plat),
|
|
.priv_auto = sizeof(struct ich_spi_priv),
|
|
.child_pre_probe = ich_spi_child_pre_probe,
|
|
.probe = ich_spi_probe,
|
|
.remove = ich_spi_remove,
|
|
.flags = DM_FLAG_OS_PREPARE,
|
|
};
|