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![Simon Glass](/assets/img/avatar_default.png)
This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
446 lines
9.8 KiB
C
446 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019
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* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <init.h>
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#include <log.h>
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#include <ram.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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/* SDRAM Command Code */
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#define SD_CC_ARD 0x0 /* Master Bus (AXI) command - Read */
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#define SD_CC_AWR 0x1 /* Master Bus (AXI) command - Write */
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#define SD_CC_IRD 0x8 /* IP command - Read */
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#define SD_CC_IWR 0x9 /* IP command - Write */
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#define SD_CC_IMS 0xA /* IP command - Set Mode Register */
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#define SD_CC_IACT 0xB /* IP command - ACTIVE */
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#define SD_CC_IAF 0xC /* IP command - Auto Refresh */
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#define SD_CC_ISF 0xD /* IP Command - Self Refresh */
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#define SD_CC_IPRE 0xE /* IP command - Precharge */
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#define SD_CC_IPREA 0xF /* IP command - Precharge ALL */
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#define SEMC_MCR_MDIS BIT(1)
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#define SEMC_MCR_DQSMD BIT(2)
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#define SEMC_INTR_IPCMDERR BIT(1)
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#define SEMC_INTR_IPCMDDONE BIT(0)
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#define SEMC_IPCMD_KEY 0xA55A0000
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struct imxrt_semc_regs {
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/* 0x0 */
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u32 mcr;
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u32 iocr;
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u32 bmcr0;
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u32 bmcr1;
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u32 br[9];
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/* 0x34 */
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u32 res1;
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u32 inten;
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u32 intr;
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/* 0x40 */
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u32 sdramcr0;
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u32 sdramcr1;
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u32 sdramcr2;
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u32 sdramcr3;
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/* 0x50 */
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u32 nandcr0;
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u32 nandcr1;
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u32 nandcr2;
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u32 nandcr3;
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/* 0x60 */
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u32 norcr0;
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u32 norcr1;
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u32 norcr2;
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u32 norcr3;
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/* 0x70 */
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u32 sramcr0;
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u32 sramcr1;
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u32 sramcr2;
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u32 sramcr3;
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/* 0x80 */
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u32 dbicr0;
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u32 dbicr1;
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u32 res2[2];
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/* 0x90 */
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u32 ipcr0;
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u32 ipcr1;
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u32 ipcr2;
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u32 ipcmd;
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/* 0xA0 */
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u32 iptxdat;
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u32 res3[3];
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/* 0xB0 */
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u32 iprxdat;
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u32 res4[3];
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/* 0xC0 */
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u32 sts[16];
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};
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#define SEMC_IOCR_MUX_A8_SHIFT 0
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#define SEMC_IOCR_MUX_CSX0_SHIFT 3
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#define SEMC_IOCR_MUX_CSX1_SHIFT 6
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#define SEMC_IOCR_MUX_CSX2_SHIFT 9
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#define SEMC_IOCR_MUX_CSX3_SHIFT 12
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#define SEMC_IOCR_MUX_RDY_SHIFT 15
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struct imxrt_sdram_mux {
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u8 a8;
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u8 csx0;
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u8 csx1;
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u8 csx2;
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u8 csx3;
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u8 rdy;
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};
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#define SEMC_SDRAMCR0_PS_SHIFT 0
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#define SEMC_SDRAMCR0_BL_SHIFT 4
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#define SEMC_SDRAMCR0_COL_SHIFT 8
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#define SEMC_SDRAMCR0_CL_SHIFT 10
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struct imxrt_sdram_control {
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u8 memory_width;
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u8 burst_len;
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u8 no_columns;
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u8 cas_latency;
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};
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#define SEMC_SDRAMCR1_PRE2ACT_SHIFT 0
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#define SEMC_SDRAMCR1_ACT2RW_SHIFT 4
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#define SEMC_SDRAMCR1_RFRC_SHIFT 8
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#define SEMC_SDRAMCR1_WRC_SHIFT 13
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#define SEMC_SDRAMCR1_CKEOFF_SHIFT 16
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#define SEMC_SDRAMCR1_ACT2PRE_SHIFT 20
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#define SEMC_SDRAMCR2_SRRC_SHIFT 0
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#define SEMC_SDRAMCR2_REF2REF_SHIFT 8
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#define SEMC_SDRAMCR2_ACT2ACT_SHIFT 16
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#define SEMC_SDRAMCR2_ITO_SHIFT 24
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#define SEMC_SDRAMCR3_REN BIT(0)
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#define SEMC_SDRAMCR3_REBL_SHIFT 1
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#define SEMC_SDRAMCR3_PRESCALE_SHIFT 8
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#define SEMC_SDRAMCR3_RT_SHIFT 16
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#define SEMC_SDRAMCR3_UT_SHIFT 24
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struct imxrt_sdram_timing {
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u8 pre2act;
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u8 act2rw;
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u8 rfrc;
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u8 wrc;
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u8 ckeoff;
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u8 act2pre;
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u8 srrc;
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u8 ref2ref;
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u8 act2act;
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u8 ito;
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u8 rebl;
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u8 prescale;
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u8 rt;
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u8 ut;
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};
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enum imxrt_semc_bank {
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SDRAM_BANK1,
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SDRAM_BANK2,
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SDRAM_BANK3,
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SDRAM_BANK4,
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MAX_SDRAM_BANK,
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};
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#define SEMC_BR_VLD_MASK 1
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#define SEMC_BR_MS_SHIFT 1
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struct bank_params {
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enum imxrt_semc_bank target_bank;
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u32 base_address;
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u32 memory_size;
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};
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struct imxrt_sdram_params {
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struct imxrt_semc_regs *base;
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struct imxrt_sdram_mux *sdram_mux;
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struct imxrt_sdram_control *sdram_control;
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struct imxrt_sdram_timing *sdram_timing;
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struct bank_params bank_params[MAX_SDRAM_BANK];
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u8 no_sdram_banks;
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};
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static int imxrt_sdram_wait_ipcmd_done(struct imxrt_semc_regs *regs)
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{
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do {
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readl(®s->intr);
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if (regs->intr & SEMC_INTR_IPCMDDONE)
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return 0;
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if (regs->intr & SEMC_INTR_IPCMDERR)
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return -EIO;
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mdelay(50);
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} while (1);
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}
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static int imxrt_sdram_ipcmd(struct imxrt_semc_regs *regs, u32 mem_addr,
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u32 ipcmd, u32 wd, u32 *rd)
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{
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int ret;
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if (ipcmd == SD_CC_IWR || ipcmd == SD_CC_IMS)
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writel(wd, ®s->iptxdat);
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/* set slave address for every command as specified on RM */
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writel(mem_addr, ®s->ipcr0);
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/* execute command */
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writel(SEMC_IPCMD_KEY | ipcmd, ®s->ipcmd);
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ret = imxrt_sdram_wait_ipcmd_done(regs);
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if (ret < 0)
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return ret;
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if (ipcmd == SD_CC_IRD) {
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if (!rd)
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return -EINVAL;
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*rd = readl(®s->iprxdat);
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}
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return 0;
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}
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int imxrt_sdram_init(struct udevice *dev)
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{
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struct imxrt_sdram_params *params = dev_get_plat(dev);
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struct imxrt_sdram_mux *mux = params->sdram_mux;
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struct imxrt_sdram_control *ctrl = params->sdram_control;
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struct imxrt_sdram_timing *time = params->sdram_timing;
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struct imxrt_semc_regs *regs = params->base;
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struct bank_params *bank_params;
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u32 rd;
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int i;
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/* enable the SEMC controller */
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clrbits_le32(®s->mcr, SEMC_MCR_MDIS);
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/* set DQS mode from DQS pad */
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setbits_le32(®s->mcr, SEMC_MCR_DQSMD);
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for (i = 0, bank_params = params->bank_params;
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i < params->no_sdram_banks; bank_params++,
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i++)
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writel((bank_params->base_address & 0xfffff000)
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| bank_params->memory_size << SEMC_BR_MS_SHIFT
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| SEMC_BR_VLD_MASK,
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®s->br[bank_params->target_bank]);
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writel(mux->a8 << SEMC_IOCR_MUX_A8_SHIFT
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| mux->csx0 << SEMC_IOCR_MUX_CSX0_SHIFT
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| mux->csx1 << SEMC_IOCR_MUX_CSX1_SHIFT
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| mux->csx2 << SEMC_IOCR_MUX_CSX2_SHIFT
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| mux->csx3 << SEMC_IOCR_MUX_CSX3_SHIFT
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| mux->rdy << SEMC_IOCR_MUX_RDY_SHIFT,
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®s->iocr);
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writel(ctrl->memory_width << SEMC_SDRAMCR0_PS_SHIFT
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| ctrl->burst_len << SEMC_SDRAMCR0_BL_SHIFT
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| ctrl->no_columns << SEMC_SDRAMCR0_COL_SHIFT
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| ctrl->cas_latency << SEMC_SDRAMCR0_CL_SHIFT,
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®s->sdramcr0);
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writel(time->pre2act << SEMC_SDRAMCR1_PRE2ACT_SHIFT
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| time->act2rw << SEMC_SDRAMCR1_ACT2RW_SHIFT
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| time->rfrc << SEMC_SDRAMCR1_RFRC_SHIFT
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| time->wrc << SEMC_SDRAMCR1_WRC_SHIFT
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| time->ckeoff << SEMC_SDRAMCR1_CKEOFF_SHIFT
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| time->act2pre << SEMC_SDRAMCR1_ACT2PRE_SHIFT,
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®s->sdramcr1);
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writel(time->srrc << SEMC_SDRAMCR2_SRRC_SHIFT
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| time->ref2ref << SEMC_SDRAMCR2_REF2REF_SHIFT
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| time->act2act << SEMC_SDRAMCR2_ACT2ACT_SHIFT
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| time->ito << SEMC_SDRAMCR2_ITO_SHIFT,
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®s->sdramcr2);
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writel(time->rebl << SEMC_SDRAMCR3_REBL_SHIFT
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| time->prescale << SEMC_SDRAMCR3_PRESCALE_SHIFT
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| time->rt << SEMC_SDRAMCR3_RT_SHIFT
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| time->ut << SEMC_SDRAMCR3_UT_SHIFT
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| SEMC_SDRAMCR3_REN,
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®s->sdramcr3);
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writel(2, ®s->ipcr1);
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for (i = 0, bank_params = params->bank_params;
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i < params->no_sdram_banks; bank_params++,
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i++) {
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mdelay(250);
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imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IPREA,
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0, &rd);
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imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF,
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0, &rd);
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imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF,
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0, &rd);
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imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IMS,
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ctrl->burst_len | (ctrl->cas_latency << 4),
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&rd);
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mdelay(250);
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}
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return 0;
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}
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static int imxrt_semc_of_to_plat(struct udevice *dev)
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{
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struct imxrt_sdram_params *params = dev_get_plat(dev);
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ofnode bank_node;
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u8 bank = 0;
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params->sdram_mux =
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(struct imxrt_sdram_mux *)
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dev_read_u8_array_ptr(dev,
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"fsl,sdram-mux",
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sizeof(struct imxrt_sdram_mux));
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if (!params->sdram_mux) {
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pr_err("fsl,sdram-mux not found");
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return -EINVAL;
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}
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params->sdram_control =
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(struct imxrt_sdram_control *)
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dev_read_u8_array_ptr(dev,
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"fsl,sdram-control",
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sizeof(struct imxrt_sdram_control));
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if (!params->sdram_control) {
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pr_err("fsl,sdram-control not found");
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return -EINVAL;
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}
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params->sdram_timing =
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(struct imxrt_sdram_timing *)
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dev_read_u8_array_ptr(dev,
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"fsl,sdram-timing",
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sizeof(struct imxrt_sdram_timing));
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if (!params->sdram_timing) {
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pr_err("fsl,sdram-timing not found");
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return -EINVAL;
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}
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dev_for_each_subnode(bank_node, dev) {
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struct bank_params *bank_params;
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char *bank_name;
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int ret;
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/* extract the bank index from DT */
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bank_name = (char *)ofnode_get_name(bank_node);
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strsep(&bank_name, "@");
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if (!bank_name) {
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pr_err("missing sdram bank index");
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return -EINVAL;
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}
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bank_params = ¶ms->bank_params[bank];
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strict_strtoul(bank_name, 10,
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(unsigned long *)&bank_params->target_bank);
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if (bank_params->target_bank >= MAX_SDRAM_BANK) {
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pr_err("Found bank %d , but only bank 0,1,2,3 are supported",
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bank_params->target_bank);
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return -EINVAL;
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}
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ret = ofnode_read_u32(bank_node,
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"fsl,memory-size",
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&bank_params->memory_size);
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if (ret < 0) {
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pr_err("fsl,memory-size not found");
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return -EINVAL;
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}
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ret = ofnode_read_u32(bank_node,
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"fsl,base-address",
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&bank_params->base_address);
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if (ret < 0) {
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pr_err("fsl,base-address not found");
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return -EINVAL;
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}
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debug("Found bank %s %u\n", bank_name,
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bank_params->target_bank);
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bank++;
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}
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params->no_sdram_banks = bank;
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debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
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return 0;
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}
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static int imxrt_semc_probe(struct udevice *dev)
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{
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struct imxrt_sdram_params *params = dev_get_plat(dev);
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int ret;
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fdt_addr_t addr;
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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params->base = (struct imxrt_semc_regs *)addr;
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#ifdef CONFIG_CLK
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struct clk clk;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&clk);
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if (ret) {
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dev_err(dev, "failed to enable clock\n");
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return ret;
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}
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#endif
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ret = imxrt_sdram_init(dev);
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if (ret)
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return ret;
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return 0;
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}
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static int imxrt_semc_get_info(struct udevice *dev, struct ram_info *info)
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{
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return 0;
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}
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static struct ram_ops imxrt_semc_ops = {
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.get_info = imxrt_semc_get_info,
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};
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static const struct udevice_id imxrt_semc_ids[] = {
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{ .compatible = "fsl,imxrt-semc", .data = 0 },
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{ }
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};
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U_BOOT_DRIVER(imxrt_semc) = {
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.name = "imxrt_semc",
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.id = UCLASS_RAM,
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.of_match = imxrt_semc_ids,
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.ops = &imxrt_semc_ops,
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.of_to_plat = imxrt_semc_of_to_plat,
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.probe = imxrt_semc_probe,
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.plat_auto = sizeof(struct imxrt_sdram_params),
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};
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