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![Simon Glass](/assets/img/avatar_default.png)
At present ofnode is present in the device even if it is never used. With of-platdata this field is not used, so can be removed. In preparation for this, change the access to go through inline functions. Signed-off-by: Simon Glass <sjg@chromium.org>
417 lines
9.8 KiB
C
417 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/**
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* PCIe SERDES driver for AM654x SoC
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*
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* Copyright (C) 2018 Texas Instruments
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* Author: Kishon Vijay Abraham I <kishon@ti.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <log.h>
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#include <dm/device.h>
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#include <dm/device_compat.h>
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#include <dm/lists.h>
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#include <dt-bindings/phy/phy.h>
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#include <generic-phy.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <power-domain.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#define CMU_R07C 0x7c
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#define CMU_MASTER_CDN_O BIT(24)
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#define COMLANE_R138 0xb38
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#define CONFIG_VERSION_REG_MASK GENMASK(23, 16)
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#define CONFIG_VERSION_REG_SHIFT 16
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#define VERSION 0x70
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#define COMLANE_R190 0xb90
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#define L1_MASTER_CDN_O BIT(9)
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#define COMLANE_R194 0xb94
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#define CMU_OK_I_0 BIT(19)
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#define SERDES_CTRL 0x1fd0
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#define POR_EN BIT(29)
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#define WIZ_LANEXCTL_STS 0x1fe0
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#define TX0_ENABLE_OVL BIT(31)
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#define TX0_ENABLE_MASK GENMASK(30, 29)
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#define TX0_ENABLE_SHIFT 29
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#define TX0_DISABLE_STATE 0x0
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#define TX0_SLEEP_STATE 0x1
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#define TX0_SNOOZE_STATE 0x2
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#define TX0_ENABLE_STATE 0x3
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#define RX0_ENABLE_OVL BIT(15)
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#define RX0_ENABLE_MASK GENMASK(14, 13)
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#define RX0_ENABLE_SHIFT 13
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#define RX0_DISABLE_STATE 0x0
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#define RX0_SLEEP_STATE 0x1
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#define RX0_SNOOZE_STATE 0x2
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#define RX0_ENABLE_STATE 0x3
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#define WIZ_PLL_CTRL 0x1ff4
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#define PLL_ENABLE_OVL BIT(31)
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#define PLL_ENABLE_MASK GENMASK(30, 29)
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#define PLL_ENABLE_SHIFT 29
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#define PLL_DISABLE_STATE 0x0
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#define PLL_SLEEP_STATE 0x1
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#define PLL_SNOOZE_STATE 0x2
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#define PLL_ENABLE_STATE 0x3
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#define PLL_OK BIT(28)
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#define PLL_LOCK_TIME 1000 /* in milliseconds */
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#define SLEEP_TIME 100 /* in microseconds */
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#define LANE_USB3 0x0
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#define LANE_PCIE0_LANE0 0x1
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#define LANE_PCIE1_LANE0 0x0
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#define LANE_PCIE0_LANE1 0x1
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#define SERDES_NUM_CLOCKS 3
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/* SERDES control MMR bit offsets */
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#define SERDES_CTL_LANE_FUNC_SEL_SHIFT 0
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#define SERDES_CTL_LANE_FUNC_SEL_MASK GENMASK(1, 0)
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#define SERDES_CTL_CLK_SEL_SHIFT 4
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#define SERDES_CTL_CLK_SEL_MASK GENMASK(7, 4)
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/**
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* struct serdes_am654_mux_clk_data - clock controller information structure
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*/
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struct serdes_am654_mux_clk_data {
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struct regmap *regmap;
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struct clk_bulk parents;
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};
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static int serdes_am654_mux_clk_probe(struct udevice *dev)
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{
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struct serdes_am654_mux_clk_data *data = dev_get_priv(dev);
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struct udevice *syscon;
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struct regmap *regmap;
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int ret;
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debug("%s(dev=%s)\n", __func__, dev->name);
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if (!data)
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return -ENOMEM;
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ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
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"ti,serdes-clk", &syscon);
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if (ret) {
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dev_err(dev, "unable to find syscon device\n");
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return ret;
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}
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regmap = syscon_get_regmap(syscon);
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if (IS_ERR(regmap)) {
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dev_err(dev, "Fail to get Syscon regmap\n");
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return PTR_ERR(regmap);
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}
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data->regmap = regmap;
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ret = clk_get_bulk(dev, &data->parents);
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if (ret) {
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dev_err(dev, "Failed to obtain parent clocks\n");
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return ret;
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}
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return 0;
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}
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static int mux_table[SERDES_NUM_CLOCKS][3] = {
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/*
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* The entries represent values for selecting between
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* {left input, external reference clock, right input}
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* Only one of Left Output or Right Output should be used since
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* both left and right output clock uses the same bits and modifying
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* one clock will impact the other.
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*/
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{ BIT(2), 0, BIT(0) }, /* Mux of CMU refclk */
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{ -1, BIT(3), BIT(1) }, /* Mux of Left Output */
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{ BIT(1), BIT(3) | BIT(1), -1 }, /* Mux of Right Output */
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};
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static int serdes_am654_mux_clk_set_parent(struct clk *clk, struct clk *parent)
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{
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struct serdes_am654_mux_clk_data *data = dev_get_priv(clk->dev);
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u32 val;
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int i;
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debug("%s(clk=%s, parent=%s)\n", __func__, clk->dev->name,
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parent->dev->name);
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/*
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* Since we have the same device-tree node represent both the
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* clock and serdes device, we have two devices associated with
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* the serdes node. assigned-clocks for this node is processed twice,
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* once for the clock device and another time for the serdes
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* device. When it is processed for the clock device, it is before
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* the probe for clock device has been called. We ignore this case
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* and rely on assigned-clocks to be processed correctly for the
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* serdes case.
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*/
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if (!data->regmap)
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return 0;
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for (i = 0; i < data->parents.count; i++) {
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if (clk_is_match(&data->parents.clks[i], parent))
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break;
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}
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if (i >= data->parents.count)
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return -EINVAL;
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val = mux_table[clk->id][i];
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val <<= SERDES_CTL_CLK_SEL_SHIFT;
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regmap_update_bits(data->regmap, 0, SERDES_CTL_CLK_SEL_MASK, val);
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return 0;
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}
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static struct clk_ops serdes_am654_mux_clk_ops = {
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.set_parent = serdes_am654_mux_clk_set_parent,
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};
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U_BOOT_DRIVER(serdes_am654_mux_clk) = {
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.name = "ti-serdes-am654-mux-clk",
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.id = UCLASS_CLK,
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.probe = serdes_am654_mux_clk_probe,
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.priv_auto = sizeof(struct serdes_am654_mux_clk_data),
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.ops = &serdes_am654_mux_clk_ops,
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};
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struct serdes_am654 {
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struct regmap *regmap;
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struct regmap *serdes_ctl;
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};
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static int serdes_am654_enable_pll(struct serdes_am654 *phy)
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{
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u32 mask = PLL_ENABLE_OVL | PLL_ENABLE_MASK;
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u32 val = PLL_ENABLE_OVL | (PLL_ENABLE_STATE << PLL_ENABLE_SHIFT);
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regmap_update_bits(phy->regmap, WIZ_PLL_CTRL, mask, val);
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return regmap_read_poll_timeout(phy->regmap, WIZ_PLL_CTRL, val,
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val & PLL_OK, 1000, PLL_LOCK_TIME);
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}
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static void serdes_am654_disable_pll(struct serdes_am654 *phy)
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{
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u32 mask = PLL_ENABLE_OVL | PLL_ENABLE_MASK;
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regmap_update_bits(phy->regmap, WIZ_PLL_CTRL, mask, 0);
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}
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static int serdes_am654_enable_txrx(struct serdes_am654 *phy)
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{
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u32 mask;
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u32 val;
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/* Enable TX */
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mask = TX0_ENABLE_OVL | TX0_ENABLE_MASK;
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val = TX0_ENABLE_OVL | (TX0_ENABLE_STATE << TX0_ENABLE_SHIFT);
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regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, val);
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/* Enable RX */
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mask = RX0_ENABLE_OVL | RX0_ENABLE_MASK;
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val = RX0_ENABLE_OVL | (RX0_ENABLE_STATE << RX0_ENABLE_SHIFT);
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regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, val);
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return 0;
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}
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static int serdes_am654_disable_txrx(struct serdes_am654 *phy)
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{
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u32 mask;
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/* Disable TX */
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mask = TX0_ENABLE_OVL | TX0_ENABLE_MASK;
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regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, 0);
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/* Disable RX */
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mask = RX0_ENABLE_OVL | RX0_ENABLE_MASK;
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regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, 0);
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return 0;
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}
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static int serdes_am654_power_on(struct phy *x)
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{
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struct serdes_am654 *phy = dev_get_priv(x->dev);
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int ret;
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u32 val;
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ret = serdes_am654_enable_pll(phy);
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if (ret) {
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dev_err(x->dev, "Failed to enable PLL\n");
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return ret;
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}
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ret = serdes_am654_enable_txrx(phy);
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if (ret) {
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dev_err(x->dev, "Failed to enable TX RX\n");
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return ret;
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}
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return regmap_read_poll_timeout(phy->regmap, COMLANE_R194, val,
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val & CMU_OK_I_0, SLEEP_TIME,
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PLL_LOCK_TIME);
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}
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static int serdes_am654_power_off(struct phy *x)
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{
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struct serdes_am654 *phy = dev_get_priv(x->dev);
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serdes_am654_disable_txrx(phy);
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serdes_am654_disable_pll(phy);
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return 0;
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}
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static int serdes_am654_init(struct phy *x)
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{
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struct serdes_am654 *phy = dev_get_priv(x->dev);
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u32 mask;
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u32 val;
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mask = CONFIG_VERSION_REG_MASK;
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val = VERSION << CONFIG_VERSION_REG_SHIFT;
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regmap_update_bits(phy->regmap, COMLANE_R138, mask, val);
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val = CMU_MASTER_CDN_O;
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regmap_update_bits(phy->regmap, CMU_R07C, val, val);
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val = L1_MASTER_CDN_O;
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regmap_update_bits(phy->regmap, COMLANE_R190, val, val);
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return 0;
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}
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static int serdes_am654_reset(struct phy *x)
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{
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struct serdes_am654 *phy = dev_get_priv(x->dev);
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u32 val;
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val = POR_EN;
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regmap_update_bits(phy->regmap, SERDES_CTRL, val, val);
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mdelay(1);
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regmap_update_bits(phy->regmap, SERDES_CTRL, val, 0);
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return 0;
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}
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static int serdes_am654_of_xlate(struct phy *x,
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struct ofnode_phandle_args *args)
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{
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struct serdes_am654 *phy = dev_get_priv(x->dev);
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if (args->args_count != 2) {
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dev_err(x->dev, "Invalid DT PHY argument count: %d\n",
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args->args_count);
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return -EINVAL;
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}
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if (args->args[0] != PHY_TYPE_PCIE) {
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dev_err(x->dev, "Unrecognized PHY type: %d\n",
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args->args[0]);
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return -EINVAL;
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}
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x->id = args->args[0] | (args->args[1] << 16);
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/* Setup mux mode using second argument */
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regmap_update_bits(phy->serdes_ctl, 0, SERDES_CTL_LANE_FUNC_SEL_MASK,
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args->args[1]);
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return 0;
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}
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static int serdes_am654_bind(struct udevice *dev)
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{
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int ret;
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ret = device_bind_driver_to_node(dev->parent,
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"ti-serdes-am654-mux-clk",
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dev_read_name(dev), dev_ofnode(dev),
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NULL);
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if (ret) {
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dev_err(dev, "%s: not able to bind clock driver\n", __func__);
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return ret;
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}
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return 0;
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}
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static int serdes_am654_probe(struct udevice *dev)
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{
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struct serdes_am654 *phy = dev_get_priv(dev);
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struct power_domain serdes_pwrdmn;
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struct regmap *serdes_ctl;
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struct regmap *map;
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int ret;
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ret = regmap_init_mem(dev_ofnode(dev), &map);
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if (ret)
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return ret;
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phy->regmap = map;
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serdes_ctl = syscon_regmap_lookup_by_phandle(dev, "ti,serdes-clk");
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if (IS_ERR(serdes_ctl)) {
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dev_err(dev, "unable to find syscon device\n");
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return PTR_ERR(serdes_ctl);
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}
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phy->serdes_ctl = serdes_ctl;
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ret = power_domain_get_by_index(dev, &serdes_pwrdmn, 0);
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if (ret) {
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dev_err(dev, "failed to get power domain\n");
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return ret;
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}
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ret = power_domain_on(&serdes_pwrdmn);
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if (ret) {
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dev_err(dev, "Power domain on failed\n");
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return ret;
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}
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return 0;
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}
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static const struct udevice_id serdes_am654_phy_ids[] = {
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{
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.compatible = "ti,phy-am654-serdes",
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},
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};
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static const struct phy_ops serdes_am654_phy_ops = {
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.reset = serdes_am654_reset,
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.init = serdes_am654_init,
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.power_on = serdes_am654_power_on,
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.power_off = serdes_am654_power_off,
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.of_xlate = serdes_am654_of_xlate,
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};
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U_BOOT_DRIVER(am654_serdes_phy) = {
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.name = "am654_serdes_phy",
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.id = UCLASS_PHY,
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.of_match = serdes_am654_phy_ids,
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.bind = serdes_am654_bind,
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.ops = &serdes_am654_phy_ops,
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.probe = serdes_am654_probe,
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.priv_auto = sizeof(struct serdes_am654),
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};
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