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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-31 06:18:51 +09:00
![Simon Glass](/assets/img/avatar_default.png)
At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
604 lines
14 KiB
C
604 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019, Linaro Limited
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*/
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#include <cpu_func.h>
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#include <log.h>
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#include <malloc.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <common.h>
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#include <console.h>
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#include <linux/bitops.h>
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#include <linux/bug.h>
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#include <linux/delay.h>
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#include <linux/mii.h>
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#include <miiphy.h>
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#include <net.h>
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#include <reset.h>
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#include <wait_bit.h>
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#define STATION_ADDR_LOW 0x0000
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#define STATION_ADDR_HIGH 0x0004
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#define MAC_DUPLEX_HALF_CTRL 0x0008
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#define PORT_MODE 0x0040
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#define PORT_EN 0x0044
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#define BIT_TX_EN BIT(2)
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#define BIT_RX_EN BIT(1)
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#define MODE_CHANGE_EN 0x01b4
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#define BIT_MODE_CHANGE_EN BIT(0)
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#define MDIO_SINGLE_CMD 0x03c0
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#define BIT_MDIO_BUSY BIT(20)
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#define MDIO_READ (BIT(17) | BIT_MDIO_BUSY)
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#define MDIO_WRITE (BIT(16) | BIT_MDIO_BUSY)
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#define MDIO_SINGLE_DATA 0x03c4
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#define MDIO_RDATA_STATUS 0x03d0
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#define BIT_MDIO_RDATA_INVALID BIT(0)
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#define RX_FQ_START_ADDR 0x0500
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#define RX_FQ_DEPTH 0x0504
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#define RX_FQ_WR_ADDR 0x0508
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#define RX_FQ_RD_ADDR 0x050c
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#define RX_FQ_REG_EN 0x0518
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#define RX_BQ_START_ADDR 0x0520
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#define RX_BQ_DEPTH 0x0524
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#define RX_BQ_WR_ADDR 0x0528
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#define RX_BQ_RD_ADDR 0x052c
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#define RX_BQ_REG_EN 0x0538
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#define TX_BQ_START_ADDR 0x0580
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#define TX_BQ_DEPTH 0x0584
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#define TX_BQ_WR_ADDR 0x0588
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#define TX_BQ_RD_ADDR 0x058c
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#define TX_BQ_REG_EN 0x0598
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#define TX_RQ_START_ADDR 0x05a0
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#define TX_RQ_DEPTH 0x05a4
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#define TX_RQ_WR_ADDR 0x05a8
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#define TX_RQ_RD_ADDR 0x05ac
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#define TX_RQ_REG_EN 0x05b8
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#define BIT_START_ADDR_EN BIT(2)
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#define BIT_DEPTH_EN BIT(1)
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#define DESC_WR_RD_ENA 0x05cc
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#define BIT_RX_OUTCFF_WR BIT(3)
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#define BIT_RX_CFF_RD BIT(2)
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#define BIT_TX_OUTCFF_WR BIT(1)
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#define BIT_TX_CFF_RD BIT(0)
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#define BITS_DESC_ENA (BIT_RX_OUTCFF_WR | BIT_RX_CFF_RD | \
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BIT_TX_OUTCFF_WR | BIT_TX_CFF_RD)
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/* MACIF_CTRL */
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#define RGMII_SPEED_1000 0x2c
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#define RGMII_SPEED_100 0x2f
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#define RGMII_SPEED_10 0x2d
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#define MII_SPEED_100 0x0f
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#define MII_SPEED_10 0x0d
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#define GMAC_SPEED_1000 0x05
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#define GMAC_SPEED_100 0x01
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#define GMAC_SPEED_10 0x00
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#define GMAC_FULL_DUPLEX BIT(4)
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#define RX_DESC_NUM 64
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#define TX_DESC_NUM 2
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#define DESC_SIZE 32
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#define DESC_WORD_SHIFT 3
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#define DESC_BYTE_SHIFT 5
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#define DESC_CNT(n) ((n) >> DESC_BYTE_SHIFT)
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#define DESC_BYTE(n) ((n) << DESC_BYTE_SHIFT)
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#define DESC_VLD_FREE 0
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#define DESC_VLD_BUSY 1
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#define MAC_MAX_FRAME_SIZE 1600
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enum higmac_queue {
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RX_FQ,
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RX_BQ,
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TX_BQ,
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TX_RQ,
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};
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struct higmac_desc {
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unsigned int buf_addr;
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unsigned int buf_len:11;
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unsigned int reserve0:5;
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unsigned int data_len:11;
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unsigned int reserve1:2;
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unsigned int fl:2;
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unsigned int descvid:1;
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unsigned int reserve2[6];
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};
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struct higmac_priv {
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void __iomem *base;
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void __iomem *macif_ctrl;
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struct reset_ctl rst_phy;
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struct higmac_desc *rxfq;
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struct higmac_desc *rxbq;
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struct higmac_desc *txbq;
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struct higmac_desc *txrq;
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int rxdesc_in_use;
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struct mii_dev *bus;
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struct phy_device *phydev;
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int phyintf;
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int phyaddr;
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};
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#define flush_desc(d) flush_cache((unsigned long)(d), sizeof(*(d)))
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#define invalidate_desc(d) \
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invalidate_dcache_range((unsigned long)(d), \
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(unsigned long)(d) + sizeof(*(d)))
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static int higmac_write_hwaddr(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct higmac_priv *priv = dev_get_priv(dev);
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unsigned char *mac = pdata->enetaddr;
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u32 val;
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val = mac[1] | (mac[0] << 8);
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writel(val, priv->base + STATION_ADDR_HIGH);
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val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
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writel(val, priv->base + STATION_ADDR_LOW);
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return 0;
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}
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static int higmac_free_pkt(struct udevice *dev, uchar *packet, int length)
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{
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struct higmac_priv *priv = dev_get_priv(dev);
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/* Inform GMAC that the RX descriptor is no longer in use */
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writel(DESC_BYTE(priv->rxdesc_in_use), priv->base + RX_BQ_RD_ADDR);
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return 0;
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}
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static int higmac_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct higmac_priv *priv = dev_get_priv(dev);
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struct higmac_desc *fqd = priv->rxfq;
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struct higmac_desc *bqd = priv->rxbq;
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int fqw_pos, fqr_pos, bqw_pos, bqr_pos;
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int timeout = 100000;
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int len = 0;
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int space;
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int i;
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fqw_pos = DESC_CNT(readl(priv->base + RX_FQ_WR_ADDR));
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fqr_pos = DESC_CNT(readl(priv->base + RX_FQ_RD_ADDR));
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if (fqw_pos >= fqr_pos)
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space = RX_DESC_NUM - (fqw_pos - fqr_pos);
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else
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space = fqr_pos - fqw_pos;
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/* Leave one free to distinguish full filled from empty buffer */
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for (i = 0; i < space - 1; i++) {
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fqd = priv->rxfq + fqw_pos;
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invalidate_dcache_range(fqd->buf_addr,
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fqd->buf_addr + MAC_MAX_FRAME_SIZE);
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if (++fqw_pos >= RX_DESC_NUM)
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fqw_pos = 0;
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writel(DESC_BYTE(fqw_pos), priv->base + RX_FQ_WR_ADDR);
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}
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bqr_pos = DESC_CNT(readl(priv->base + RX_BQ_RD_ADDR));
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bqd += bqr_pos;
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/* BQ is only ever written by GMAC */
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invalidate_desc(bqd);
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do {
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bqw_pos = DESC_CNT(readl(priv->base + RX_BQ_WR_ADDR));
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udelay(1);
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} while (--timeout && bqw_pos == bqr_pos);
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if (!timeout)
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return -ETIMEDOUT;
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if (++bqr_pos >= RX_DESC_NUM)
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bqr_pos = 0;
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len = bqd->data_len;
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/* CPU should not have touched this buffer since we added it to FQ */
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invalidate_dcache_range(bqd->buf_addr, bqd->buf_addr + len);
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*packetp = (void *)(unsigned long)bqd->buf_addr;
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/* Record the RX_BQ descriptor that is holding RX data */
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priv->rxdesc_in_use = bqr_pos;
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return len;
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}
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static int higmac_send(struct udevice *dev, void *packet, int length)
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{
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struct higmac_priv *priv = dev_get_priv(dev);
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struct higmac_desc *bqd = priv->txbq;
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int bqw_pos, rqw_pos, rqr_pos;
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int timeout = 1000;
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flush_cache((unsigned long)packet, length);
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bqw_pos = DESC_CNT(readl(priv->base + TX_BQ_WR_ADDR));
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bqd += bqw_pos;
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bqd->buf_addr = (unsigned long)packet;
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bqd->descvid = DESC_VLD_BUSY;
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bqd->data_len = length;
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flush_desc(bqd);
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if (++bqw_pos >= TX_DESC_NUM)
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bqw_pos = 0;
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writel(DESC_BYTE(bqw_pos), priv->base + TX_BQ_WR_ADDR);
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rqr_pos = DESC_CNT(readl(priv->base + TX_RQ_RD_ADDR));
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if (++rqr_pos >= TX_DESC_NUM)
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rqr_pos = 0;
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do {
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rqw_pos = DESC_CNT(readl(priv->base + TX_RQ_WR_ADDR));
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udelay(1);
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} while (--timeout && rqr_pos != rqw_pos);
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if (!timeout)
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return -ETIMEDOUT;
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writel(DESC_BYTE(rqr_pos), priv->base + TX_RQ_RD_ADDR);
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return 0;
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}
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static int higmac_adjust_link(struct higmac_priv *priv)
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{
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struct phy_device *phydev = priv->phydev;
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int interface = priv->phyintf;
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u32 val;
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switch (interface) {
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case PHY_INTERFACE_MODE_RGMII:
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if (phydev->speed == SPEED_1000)
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val = RGMII_SPEED_1000;
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else if (phydev->speed == SPEED_100)
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val = RGMII_SPEED_100;
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else
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val = RGMII_SPEED_10;
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break;
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case PHY_INTERFACE_MODE_MII:
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if (phydev->speed == SPEED_100)
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val = MII_SPEED_100;
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else
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val = MII_SPEED_10;
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break;
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default:
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debug("unsupported mode: %d\n", interface);
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return -EINVAL;
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}
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if (phydev->duplex)
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val |= GMAC_FULL_DUPLEX;
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writel(val, priv->macif_ctrl);
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if (phydev->speed == SPEED_1000)
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val = GMAC_SPEED_1000;
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else if (phydev->speed == SPEED_100)
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val = GMAC_SPEED_100;
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else
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val = GMAC_SPEED_10;
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writel(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN);
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writel(val, priv->base + PORT_MODE);
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writel(0, priv->base + MODE_CHANGE_EN);
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writel(phydev->duplex, priv->base + MAC_DUPLEX_HALF_CTRL);
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return 0;
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}
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static int higmac_start(struct udevice *dev)
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{
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struct higmac_priv *priv = dev_get_priv(dev);
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struct phy_device *phydev = priv->phydev;
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int ret;
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ret = phy_startup(phydev);
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if (ret)
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return ret;
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if (!phydev->link) {
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debug("%s: link down\n", phydev->dev->name);
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return -ENODEV;
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}
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ret = higmac_adjust_link(priv);
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if (ret)
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return ret;
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/* Enable port */
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writel(BITS_DESC_ENA, priv->base + DESC_WR_RD_ENA);
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writel(BIT_TX_EN | BIT_RX_EN, priv->base + PORT_EN);
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return 0;
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}
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static void higmac_stop(struct udevice *dev)
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{
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struct higmac_priv *priv = dev_get_priv(dev);
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/* Disable port */
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writel(0, priv->base + PORT_EN);
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writel(0, priv->base + DESC_WR_RD_ENA);
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}
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static const struct eth_ops higmac_ops = {
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.start = higmac_start,
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.send = higmac_send,
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.recv = higmac_recv,
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.free_pkt = higmac_free_pkt,
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.stop = higmac_stop,
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.write_hwaddr = higmac_write_hwaddr,
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};
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static int higmac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
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{
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struct higmac_priv *priv = bus->priv;
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int ret;
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ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
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false, 1000, false);
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if (ret)
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return ret;
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writel(MDIO_READ | addr << 8 | reg, priv->base + MDIO_SINGLE_CMD);
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ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
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false, 1000, false);
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if (ret)
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return ret;
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if (readl(priv->base + MDIO_RDATA_STATUS) & BIT_MDIO_RDATA_INVALID)
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return -EINVAL;
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return readl(priv->base + MDIO_SINGLE_DATA) >> 16;
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}
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static int higmac_mdio_write(struct mii_dev *bus, int addr, int devad,
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int reg, u16 value)
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{
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struct higmac_priv *priv = bus->priv;
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int ret;
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ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
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false, 1000, false);
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if (ret)
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return ret;
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writel(value, priv->base + MDIO_SINGLE_DATA);
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writel(MDIO_WRITE | addr << 8 | reg, priv->base + MDIO_SINGLE_CMD);
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return 0;
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}
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static int higmac_init_rx_descs(struct higmac_desc *descs, int num)
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{
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int i;
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for (i = 0; i < num; i++) {
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struct higmac_desc *desc = &descs[i];
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desc->buf_addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
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MAC_MAX_FRAME_SIZE);
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if (!desc->buf_addr)
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goto free_bufs;
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desc->descvid = DESC_VLD_FREE;
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desc->buf_len = MAC_MAX_FRAME_SIZE - 1;
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flush_desc(desc);
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}
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return 0;
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free_bufs:
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while (--i > 0)
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free((void *)(unsigned long)descs[i].buf_addr);
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return -ENOMEM;
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}
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static int higmac_init_hw_queue(struct higmac_priv *priv,
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enum higmac_queue queue)
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{
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struct higmac_desc *desc, **pdesc;
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u32 regaddr, regen, regdep;
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int depth;
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int len;
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switch (queue) {
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case RX_FQ:
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regaddr = RX_FQ_START_ADDR;
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regen = RX_FQ_REG_EN;
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regdep = RX_FQ_DEPTH;
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depth = RX_DESC_NUM;
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pdesc = &priv->rxfq;
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break;
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case RX_BQ:
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regaddr = RX_BQ_START_ADDR;
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regen = RX_BQ_REG_EN;
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regdep = RX_BQ_DEPTH;
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depth = RX_DESC_NUM;
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pdesc = &priv->rxbq;
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break;
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case TX_BQ:
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regaddr = TX_BQ_START_ADDR;
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regen = TX_BQ_REG_EN;
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regdep = TX_BQ_DEPTH;
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depth = TX_DESC_NUM;
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pdesc = &priv->txbq;
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break;
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case TX_RQ:
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regaddr = TX_RQ_START_ADDR;
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regen = TX_RQ_REG_EN;
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regdep = TX_RQ_DEPTH;
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depth = TX_DESC_NUM;
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pdesc = &priv->txrq;
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break;
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}
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/* Enable depth */
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writel(BIT_DEPTH_EN, priv->base + regen);
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writel(depth << DESC_WORD_SHIFT, priv->base + regdep);
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writel(0, priv->base + regen);
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len = depth * sizeof(*desc);
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desc = memalign(ARCH_DMA_MINALIGN, len);
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if (!desc)
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return -ENOMEM;
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memset(desc, 0, len);
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flush_cache((unsigned long)desc, len);
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*pdesc = desc;
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/* Set up RX_FQ descriptors */
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if (queue == RX_FQ)
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higmac_init_rx_descs(desc, depth);
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/* Enable start address */
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writel(BIT_START_ADDR_EN, priv->base + regen);
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writel((unsigned long)desc, priv->base + regaddr);
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writel(0, priv->base + regen);
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return 0;
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}
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static int higmac_hw_init(struct higmac_priv *priv)
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{
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int ret;
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/* Initialize hardware queues */
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ret = higmac_init_hw_queue(priv, RX_FQ);
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if (ret)
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return ret;
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ret = higmac_init_hw_queue(priv, RX_BQ);
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if (ret)
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goto free_rx_fq;
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ret = higmac_init_hw_queue(priv, TX_BQ);
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if (ret)
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goto free_rx_bq;
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ret = higmac_init_hw_queue(priv, TX_RQ);
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if (ret)
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goto free_tx_bq;
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|
|
|
/* Reset phy */
|
|
reset_deassert(&priv->rst_phy);
|
|
mdelay(10);
|
|
reset_assert(&priv->rst_phy);
|
|
mdelay(30);
|
|
reset_deassert(&priv->rst_phy);
|
|
mdelay(30);
|
|
|
|
return 0;
|
|
|
|
free_tx_bq:
|
|
free(priv->txbq);
|
|
free_rx_bq:
|
|
free(priv->rxbq);
|
|
free_rx_fq:
|
|
free(priv->rxfq);
|
|
return ret;
|
|
}
|
|
|
|
static int higmac_probe(struct udevice *dev)
|
|
{
|
|
struct higmac_priv *priv = dev_get_priv(dev);
|
|
struct phy_device *phydev;
|
|
struct mii_dev *bus;
|
|
int ret;
|
|
|
|
ret = higmac_hw_init(priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
bus = mdio_alloc();
|
|
if (!bus)
|
|
return -ENOMEM;
|
|
|
|
bus->read = higmac_mdio_read;
|
|
bus->write = higmac_mdio_write;
|
|
bus->priv = priv;
|
|
priv->bus = bus;
|
|
|
|
ret = mdio_register_seq(bus, dev_seq(dev));
|
|
if (ret)
|
|
return ret;
|
|
|
|
phydev = phy_connect(bus, priv->phyaddr, dev, priv->phyintf);
|
|
if (!phydev)
|
|
return -ENODEV;
|
|
|
|
phydev->supported &= PHY_GBIT_FEATURES;
|
|
phydev->advertising = phydev->supported;
|
|
priv->phydev = phydev;
|
|
|
|
return phy_config(phydev);
|
|
}
|
|
|
|
static int higmac_remove(struct udevice *dev)
|
|
{
|
|
struct higmac_priv *priv = dev_get_priv(dev);
|
|
int i;
|
|
|
|
mdio_unregister(priv->bus);
|
|
mdio_free(priv->bus);
|
|
|
|
/* Free RX packet buffers */
|
|
for (i = 0; i < RX_DESC_NUM; i++)
|
|
free((void *)(unsigned long)priv->rxfq[i].buf_addr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int higmac_of_to_plat(struct udevice *dev)
|
|
{
|
|
struct higmac_priv *priv = dev_get_priv(dev);
|
|
int phyintf = PHY_INTERFACE_MODE_NONE;
|
|
const char *phy_mode;
|
|
ofnode phy_node;
|
|
|
|
priv->base = dev_remap_addr_index(dev, 0);
|
|
priv->macif_ctrl = dev_remap_addr_index(dev, 1);
|
|
|
|
phy_mode = dev_read_string(dev, "phy-mode");
|
|
if (phy_mode)
|
|
phyintf = phy_get_interface_by_name(phy_mode);
|
|
if (phyintf == PHY_INTERFACE_MODE_NONE)
|
|
return -ENODEV;
|
|
priv->phyintf = phyintf;
|
|
|
|
phy_node = dev_read_subnode(dev, "phy");
|
|
if (!ofnode_valid(phy_node)) {
|
|
debug("failed to find phy node\n");
|
|
return -ENODEV;
|
|
}
|
|
priv->phyaddr = ofnode_read_u32_default(phy_node, "reg", 0);
|
|
|
|
return reset_get_by_name(dev, "phy", &priv->rst_phy);
|
|
}
|
|
|
|
static const struct udevice_id higmac_ids[] = {
|
|
{ .compatible = "hisilicon,hi3798cv200-gmac" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(eth_higmac) = {
|
|
.name = "eth_higmac",
|
|
.id = UCLASS_ETH,
|
|
.of_match = higmac_ids,
|
|
.of_to_plat = higmac_of_to_plat,
|
|
.probe = higmac_probe,
|
|
.remove = higmac_remove,
|
|
.ops = &higmac_ops,
|
|
.priv_auto = sizeof(struct higmac_priv),
|
|
.plat_auto = sizeof(struct eth_pdata),
|
|
};
|