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![Simon Glass](/assets/img/avatar_default.png)
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
601 lines
15 KiB
C
601 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* Conversion to DM
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* (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com>
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*/
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#include <common.h>
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#include <env.h>
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#include <hang.h>
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#include <malloc.h>
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#include <command.h>
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#include <config.h>
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#include <net.h>
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#include <miiphy.h>
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#include <asm/global_data.h>
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#include <linux/delay.h>
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#include <linux/mii.h>
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#include <asm/immap.h>
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#include <asm/fsl_mcdmafec.h>
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#include "MCD_dma.h"
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#undef ET_DEBUG
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#undef MII_DEBUG
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/* Ethernet Transmit and Receive Buffers */
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#define DBUF_LENGTH 1520
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#define PKT_MAXBUF_SIZE 1518
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#define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
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/* RxBD bits definitions */
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#define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
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BD_ENET_RX_OV | BD_ENET_RX_TR)
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DECLARE_GLOBAL_DATA_PTR;
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static void init_eth_info(struct fec_info_dma *info)
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{
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/* setup Receive and Transmit buffer descriptor */
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#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
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static u32 tmp;
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if (info->index == 0)
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tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
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else
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info->rxbd = (cbd_t *)DBUF_LENGTH;
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info->rxbd = (cbd_t *)((u32)info->rxbd + tmp);
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tmp = (u32)info->rxbd;
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info->txbd =
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(cbd_t *)((u32)info->txbd + tmp +
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(PKTBUFSRX * sizeof(cbd_t)));
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tmp = (u32)info->txbd;
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info->txbuf =
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(char *)((u32)info->txbuf + tmp +
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(CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
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tmp = (u32)info->txbuf;
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#else
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info->rxbd =
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(cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
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(PKTBUFSRX * sizeof(cbd_t)));
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info->txbd =
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(cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
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(CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
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info->txbuf =
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(char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
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#endif
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#ifdef ET_DEBUG
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printf("rxbd %x txbd %x\n", (int)info->rxbd, (int)info->txbd);
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#endif
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info->phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
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}
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static void fec_halt(struct udevice *dev)
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{
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struct fec_info_dma *info = dev_get_priv(dev);
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volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
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int counter = 0xffff;
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/* issue graceful stop command to the FEC transmitter if necessary */
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fecp->tcr |= FEC_TCR_GTS;
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/* wait for graceful stop to register */
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while ((counter--) && (!(fecp->eir & FEC_EIR_GRA)))
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;
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/* Disable DMA tasks */
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MCD_killDma(info->tx_task);
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MCD_killDma(info->rx_task);
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/* Disable the Ethernet Controller */
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fecp->ecr &= ~FEC_ECR_ETHER_EN;
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/* Clear FIFO status registers */
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fecp->rfsr &= FIFO_ERRSTAT;
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fecp->tfsr &= FIFO_ERRSTAT;
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fecp->frst = 0x01000000;
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/* Issue a reset command to the FEC chip */
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fecp->ecr |= FEC_ECR_RESET;
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/* wait at least 20 clock cycles */
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mdelay(10);
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#ifdef ET_DEBUG
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printf("Ethernet task stopped\n");
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#endif
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}
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#ifdef ET_DEBUG
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static void dbg_fec_regs(struct eth_device *dev)
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{
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struct fec_info_dma *info = dev->priv;
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volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
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printf("=====\n");
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printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
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printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
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printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
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printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
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printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
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printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
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printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
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printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
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printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
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printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
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printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
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printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
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printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
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printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
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printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
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printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
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printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
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printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
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printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
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printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
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printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
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printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
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printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
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printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
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printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
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printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
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printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
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printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
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printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
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printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
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printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
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printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
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printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
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printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
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printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
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}
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#endif
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static void set_fec_duplex_speed(volatile fecdma_t *fecp, int dup_spd)
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{
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struct bd_info *bd = gd->bd;
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if ((dup_spd >> 16) == FULL) {
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/* Set maximum frame length */
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fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
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FEC_RCR_PROM | 0x100;
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fecp->tcr = FEC_TCR_FDEN;
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} else {
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/* Half duplex mode */
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fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
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FEC_RCR_MII_MODE | FEC_RCR_DRT;
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fecp->tcr &= ~FEC_TCR_FDEN;
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}
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if ((dup_spd & 0xFFFF) == _100BASET) {
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#ifdef MII_DEBUG
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printf("100Mbps\n");
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#endif
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bd->bi_ethspeed = 100;
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} else {
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#ifdef MII_DEBUG
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printf("10Mbps\n");
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#endif
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bd->bi_ethspeed = 10;
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}
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}
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static void fec_set_hwaddr(volatile fecdma_t *fecp, u8 *mac)
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{
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u8 curr_byte; /* byte for which to compute the CRC */
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int byte; /* loop - counter */
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int bit; /* loop - counter */
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u32 crc = 0xffffffff; /* initial value */
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for (byte = 0; byte < 6; byte++) {
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curr_byte = mac[byte];
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for (bit = 0; bit < 8; bit++) {
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if ((curr_byte & 0x01) ^ (crc & 0x01)) {
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crc >>= 1;
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crc = crc ^ 0xedb88320;
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} else {
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crc >>= 1;
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}
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curr_byte >>= 1;
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}
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}
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crc = crc >> 26;
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/* Set individual hash table register */
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if (crc >= 32) {
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fecp->ialr = (1 << (crc - 32));
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fecp->iaur = 0;
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} else {
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fecp->ialr = 0;
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fecp->iaur = (1 << crc);
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}
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/* Set physical address */
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fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
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fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
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/* Clear multicast address hash table */
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fecp->gaur = 0;
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fecp->galr = 0;
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}
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static int fec_init(struct udevice *dev)
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{
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struct fec_info_dma *info = dev_get_priv(dev);
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volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
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int rval, i;
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uchar enetaddr[6];
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#ifdef ET_DEBUG
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printf("fec_init: iobase 0x%08x ...\n", info->iobase);
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#endif
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fecpin_setclear(info, 1);
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fec_halt(dev);
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#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
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defined (CONFIG_SYS_DISCOVER_PHY)
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mii_init();
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set_fec_duplex_speed(fecp, info->dup_spd);
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#else
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#ifndef CONFIG_SYS_DISCOVER_PHY
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set_fec_duplex_speed(fecp, (FECDUPLEX << 16) | FECSPEED);
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#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
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#endif /* CONFIG_CMD_MII || CONFIG_MII */
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/* We use strictly polling mode only */
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fecp->eimr = 0;
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/* Clear any pending interrupt */
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fecp->eir = 0xffffffff;
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/* Set station address */
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if (info->index == 0)
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rval = eth_env_get_enetaddr("ethaddr", enetaddr);
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else
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rval = eth_env_get_enetaddr("eth1addr", enetaddr);
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if (!rval) {
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puts("Please set a valid MAC address\n");
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return -EINVAL;
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}
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fec_set_hwaddr(fecp, enetaddr);
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/* Set Opcode/Pause Duration Register */
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fecp->opd = 0x00010020;
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/* Setup Buffers and Buffer Descriptors */
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info->rx_idx = 0;
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info->tx_idx = 0;
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/* Setup Receiver Buffer Descriptors (13.14.24.18)
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* Settings: Empty, Wrap */
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for (i = 0; i < PKTBUFSRX; i++) {
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info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
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info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
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info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
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}
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info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
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/* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
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* Settings: Last, Tx CRC */
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for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
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info->txbd[i].cbd_sc = 0;
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info->txbd[i].cbd_datlen = 0;
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info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
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}
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info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
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info->used_tbd_idx = 0;
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info->clean_tbd_num = CONFIG_SYS_TX_ETH_BUFFER;
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/* Set Rx FIFO alarm and granularity value */
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fecp->rfcr = 0x0c000000;
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fecp->rfar = 0x0000030c;
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/* Set Tx FIFO granularity value */
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fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
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fecp->tfar = 0x00000080;
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fecp->tfwr = 0x2;
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fecp->ctcwr = 0x03000000;
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/* Enable DMA receive task */
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MCD_startDma(info->rx_task,
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(s8 *)info->rxbd,
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0,
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(s8 *)&fecp->rfdr,
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4,
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0,
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4,
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info->rx_init,
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info->rx_pri,
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(MCD_FECRX_DMA | MCD_TT_FLAGS_DEF),
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(MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
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);
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/* Enable DMA tx task with no ready buffer descriptors */
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MCD_startDma(info->tx_task,
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(s8 *)info->txbd,
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0,
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(s8 *)&fecp->tfdr,
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4,
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0,
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4,
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info->tx_init,
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info->tx_pri,
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(MCD_FECTX_DMA | MCD_TT_FLAGS_DEF),
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(MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
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);
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/* Now enable the transmit and receive processing */
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fecp->ecr |= FEC_ECR_ETHER_EN;
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return 0;
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}
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static int mcdmafec_init(struct udevice *dev)
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{
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return fec_init(dev);
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}
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static int mcdmafec_send(struct udevice *dev, void *packet, int length)
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{
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struct fec_info_dma *info = dev_get_priv(dev);
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cbd_t *p_tbd, *p_used_tbd;
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u16 phy_status;
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miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
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/* process all the consumed TBDs */
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while (info->clean_tbd_num < CONFIG_SYS_TX_ETH_BUFFER) {
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p_used_tbd = &info->txbd[info->used_tbd_idx];
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if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) {
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#ifdef ET_DEBUG
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printf("Cannot clean TBD %d, in use\n",
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info->clean_tbd_num);
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#endif
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return 0;
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}
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/* clean this buffer descriptor */
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if (info->used_tbd_idx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
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p_used_tbd->cbd_sc = BD_ENET_TX_WRAP;
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else
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p_used_tbd->cbd_sc = 0;
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/* update some indeces for a correct handling of TBD ring */
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info->clean_tbd_num++;
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info->used_tbd_idx = (info->used_tbd_idx + 1)
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% CONFIG_SYS_TX_ETH_BUFFER;
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}
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/* Check for valid length of data. */
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if (length > 1500 || length <= 0)
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return -1;
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/* Check the number of vacant TxBDs. */
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if (info->clean_tbd_num < 1) {
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printf("No available TxBDs ...\n");
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return -1;
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}
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/* Get the first TxBD to send the mac header */
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p_tbd = &info->txbd[info->tx_idx];
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p_tbd->cbd_datlen = length;
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p_tbd->cbd_bufaddr = (u32)packet;
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p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
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info->tx_idx = (info->tx_idx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
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/* Enable DMA transmit task */
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MCD_continDma(info->tx_task);
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info->clean_tbd_num -= 1;
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/* wait until frame is sent . */
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while (p_tbd->cbd_sc & BD_ENET_TX_READY)
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udelay(10);
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return (int)(info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_STATS);
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}
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static int mcdmafec_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct fec_info_dma *info = dev_get_priv(dev);
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volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
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cbd_t *prbd = &info->rxbd[info->rx_idx];
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u32 ievent;
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int frame_length, len = 0;
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/* Check if any critical events have happened */
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ievent = fecp->eir;
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if (ievent != 0) {
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fecp->eir = ievent;
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if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
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printf("fec_recv: error\n");
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fec_halt(dev);
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fec_init(dev);
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return 0;
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}
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|
if (ievent & FEC_EIR_HBERR) {
|
|
/* Heartbeat error */
|
|
fecp->tcr |= FEC_TCR_GTS;
|
|
}
|
|
|
|
if (ievent & FEC_EIR_GRA) {
|
|
/* Graceful stop complete */
|
|
if (fecp->tcr & FEC_TCR_GTS) {
|
|
printf("fec_recv: tcr_gts\n");
|
|
fec_halt(dev);
|
|
fecp->tcr &= ~FEC_TCR_GTS;
|
|
fec_init(dev);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
|
|
if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
|
|
!(prbd->cbd_sc & BD_ENET_RX_ERR) &&
|
|
((prbd->cbd_datlen - 4) > 14)) {
|
|
/* Get buffer address and size */
|
|
frame_length = prbd->cbd_datlen - 4;
|
|
|
|
/* Fill the buffer and pass it to upper layers */
|
|
net_process_received_packet((uchar *)prbd->cbd_bufaddr,
|
|
frame_length);
|
|
len = frame_length;
|
|
}
|
|
|
|
/* Reset buffer descriptor as empty */
|
|
if (info->rx_idx == (PKTBUFSRX - 1))
|
|
prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
|
|
else
|
|
prbd->cbd_sc = BD_ENET_RX_EMPTY;
|
|
|
|
prbd->cbd_datlen = PKTSIZE_ALIGN;
|
|
|
|
/* Now, we have an empty RxBD, restart the DMA receive task */
|
|
MCD_continDma(info->rx_task);
|
|
|
|
/* Increment BD count */
|
|
info->rx_idx = (info->rx_idx + 1) % PKTBUFSRX;
|
|
}
|
|
|
|
return len;
|
|
}
|
|
|
|
static void mcdmafec_halt(struct udevice *dev)
|
|
{
|
|
fec_halt(dev);
|
|
}
|
|
|
|
static const struct eth_ops mcdmafec_ops = {
|
|
.start = mcdmafec_init,
|
|
.send = mcdmafec_send,
|
|
.recv = mcdmafec_recv,
|
|
.stop = mcdmafec_halt,
|
|
};
|
|
|
|
/*
|
|
* Boot sequence, called just after mcffec_of_to_plat,
|
|
* as DM way, it replaces old mcffec_initialize.
|
|
*/
|
|
static int mcdmafec_probe(struct udevice *dev)
|
|
{
|
|
struct fec_info_dma *info = dev_get_priv(dev);
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
int node = dev_of_offset(dev);
|
|
int retval;
|
|
const u32 *val;
|
|
|
|
info->index = dev_seq(dev);
|
|
info->iobase = pdata->iobase;
|
|
info->miibase = pdata->iobase;
|
|
info->phy_addr = -1;
|
|
|
|
val = fdt_getprop(gd->fdt_blob, node, "rx-task", NULL);
|
|
if (val)
|
|
info->rx_task = fdt32_to_cpu(*val);
|
|
|
|
val = fdt_getprop(gd->fdt_blob, node, "tx-task", NULL);
|
|
if (val)
|
|
info->tx_task = fdt32_to_cpu(*val);
|
|
|
|
val = fdt_getprop(gd->fdt_blob, node, "rx-prioprity", NULL);
|
|
if (val)
|
|
info->rx_pri = fdt32_to_cpu(*val);
|
|
|
|
val = fdt_getprop(gd->fdt_blob, node, "tx-prioprity", NULL);
|
|
if (val)
|
|
info->tx_pri = fdt32_to_cpu(*val);
|
|
|
|
val = fdt_getprop(gd->fdt_blob, node, "rx-init", NULL);
|
|
if (val)
|
|
info->rx_init = fdt32_to_cpu(*val);
|
|
|
|
val = fdt_getprop(gd->fdt_blob, node, "tx-init", NULL);
|
|
if (val)
|
|
info->tx_init = fdt32_to_cpu(*val);
|
|
|
|
#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
|
|
u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
|
|
#endif
|
|
init_eth_info(info);
|
|
|
|
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
|
|
info->bus = mdio_alloc();
|
|
if (!info->bus)
|
|
return -ENOMEM;
|
|
strncpy(info->bus->name, dev->name, MDIO_NAME_LEN);
|
|
info->bus->read = mcffec_miiphy_read;
|
|
info->bus->write = mcffec_miiphy_write;
|
|
|
|
retval = mdio_register(info->bus);
|
|
if (retval < 0)
|
|
return retval;
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mcdmafec_remove(struct udevice *dev)
|
|
{
|
|
struct fec_info_dma *priv = dev_get_priv(dev);
|
|
|
|
mdio_unregister(priv->bus);
|
|
mdio_free(priv->bus);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Boot sequence, called 1st
|
|
*/
|
|
static int mcdmafec_of_to_plat(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
const u32 *val;
|
|
|
|
pdata->iobase = dev_read_addr(dev);
|
|
/* Default to 10Mbit/s */
|
|
pdata->max_speed = 10;
|
|
|
|
val = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
|
|
if (val)
|
|
pdata->max_speed = fdt32_to_cpu(*val);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id mcdmafec_ids[] = {
|
|
{ .compatible = "fsl,mcf-dma-fec" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(mcffec) = {
|
|
.name = "mcdmafec",
|
|
.id = UCLASS_ETH,
|
|
.of_match = mcdmafec_ids,
|
|
.of_to_plat = mcdmafec_of_to_plat,
|
|
.probe = mcdmafec_probe,
|
|
.remove = mcdmafec_remove,
|
|
.ops = &mcdmafec_ops,
|
|
.priv_auto = sizeof(struct fec_info_dma),
|
|
.plat_auto = sizeof(struct eth_pdata),
|
|
};
|