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![Simon Glass](/assets/img/avatar_default.png)
Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
1018 lines
25 KiB
C
1018 lines
25 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <cpu_func.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <net.h>
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#include <netdev.h>
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#include <pci.h>
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#include <linux/delay.h>
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/* Ethernet chip registers. */
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#define SCB_STATUS 0 /* Rx/Command Unit Status *Word* */
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#define SCB_INT_ACK_BYTE 1 /* Rx/Command Unit STAT/ACK byte */
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#define SCB_CMD 2 /* Rx/Command Unit Command *Word* */
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#define SCB_INTR_CTL_BYTE 3 /* Rx/Command Unit Intr.Control Byte */
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#define SCB_POINTER 4 /* General purpose pointer. */
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#define SCB_PORT 8 /* Misc. commands and operands. */
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#define SCB_FLASH 12 /* Flash memory control. */
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#define SCB_EEPROM 14 /* EEPROM memory control. */
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#define SCB_CTRL_MDI 16 /* MDI interface control. */
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#define SCB_EARLY_RX 20 /* Early receive byte count. */
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#define SCB_GEN_CONTROL 28 /* 82559 General Control Register */
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#define SCB_GEN_STATUS 29 /* 82559 General Status register */
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/* 82559 SCB status word defnitions */
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#define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
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#define SCB_STATUS_FR 0x4000 /* frame received */
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#define SCB_STATUS_CNA 0x2000 /* CU left active state */
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#define SCB_STATUS_RNR 0x1000 /* receiver left ready state */
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#define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */
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#define SCB_STATUS_SWI 0x0400 /* software generated interrupt */
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#define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */
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#define SCB_INTACK_MASK 0xFD00 /* all the above */
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#define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
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#define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
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/* System control block commands */
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/* CU Commands */
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#define CU_NOP 0x0000
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#define CU_START 0x0010
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#define CU_RESUME 0x0020
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#define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */
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#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
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#define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */
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#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
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/* RUC Commands */
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#define RUC_NOP 0x0000
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#define RUC_START 0x0001
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#define RUC_RESUME 0x0002
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#define RUC_ABORT 0x0004
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#define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */
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#define RUC_RESUMENR 0x0007
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#define CU_CMD_MASK 0x00f0
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#define RU_CMD_MASK 0x0007
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#define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */
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#define SCB_SWI 0x0200 /* 1 - cause device to interrupt */
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#define CU_STATUS_MASK 0x00C0
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#define RU_STATUS_MASK 0x003C
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#define RU_STATUS_IDLE (0 << 2)
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#define RU_STATUS_SUS (1 << 2)
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#define RU_STATUS_NORES (2 << 2)
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#define RU_STATUS_READY (4 << 2)
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#define RU_STATUS_NO_RBDS_SUS ((1 << 2) | (8 << 2))
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#define RU_STATUS_NO_RBDS_NORES ((2 << 2) | (8 << 2))
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#define RU_STATUS_NO_RBDS_READY ((4 << 2) | (8 << 2))
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/* 82559 Port interface commands. */
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#define I82559_RESET 0x00000000 /* Software reset */
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#define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */
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#define I82559_SELECTIVE_RESET 0x00000002
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#define I82559_DUMP 0x00000003
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#define I82559_DUMP_WAKEUP 0x00000007
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/* 82559 Eeprom interface. */
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#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
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#define EE_CS 0x02 /* EEPROM chip select. */
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#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
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#define EE_WRITE_0 0x01
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#define EE_WRITE_1 0x05
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#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
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#define EE_ENB (0x4800 | EE_CS)
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#define EE_CMD_BITS 3
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#define EE_DATA_BITS 16
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/* The EEPROM commands include the alway-set leading bit. */
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#define EE_EWENB_CMD(addr_len) (4 << (addr_len))
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#define EE_WRITE_CMD(addr_len) (5 << (addr_len))
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#define EE_READ_CMD(addr_len) (6 << (addr_len))
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#define EE_ERASE_CMD(addr_len) (7 << (addr_len))
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/* Receive frame descriptors. */
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struct eepro100_rxfd {
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u16 status;
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u16 control;
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u32 link; /* struct eepro100_rxfd * */
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u32 rx_buf_addr; /* void * */
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u32 count;
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u8 data[PKTSIZE_ALIGN];
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};
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#define RFD_STATUS_C 0x8000 /* completion of received frame */
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#define RFD_STATUS_OK 0x2000 /* frame received with no errors */
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#define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */
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#define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */
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#define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */
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#define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */
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#define RFD_COUNT_MASK 0x3fff
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#define RFD_COUNT_F 0x4000
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#define RFD_COUNT_EOF 0x8000
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#define RFD_RX_CRC 0x0800 /* crc error */
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#define RFD_RX_ALIGNMENT 0x0400 /* alignment error */
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#define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */
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#define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */
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#define RFD_RX_SHORT 0x0080 /* short frame error */
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#define RFD_RX_LENGTH 0x0020
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#define RFD_RX_ERROR 0x0010 /* receive error */
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#define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */
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#define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
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#define RFD_RX_TCO 0x0001 /* TCO indication */
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/* Transmit frame descriptors */
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struct eepro100_txfd { /* Transmit frame descriptor set. */
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u16 status;
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u16 command;
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u32 link; /* void * */
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u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */
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s32 count;
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u32 tx_buf_addr0; /* void *, frame to be transmitted. */
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s32 tx_buf_size0; /* Length of Tx frame. */
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u32 tx_buf_addr1; /* void *, frame to be transmitted. */
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s32 tx_buf_size1; /* Length of Tx frame. */
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};
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#define TXCB_CMD_TRANSMIT 0x0004 /* transmit command */
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#define TXCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
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#define TXCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
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#define TXCB_CMD_I 0x2000 /* generate interrupt on completion */
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#define TXCB_CMD_S 0x4000 /* suspend on completion */
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#define TXCB_CMD_EL 0x8000 /* last command block in CBL */
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#define TXCB_COUNT_MASK 0x3fff
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#define TXCB_COUNT_EOF 0x8000
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/* The Speedo3 Rx and Tx frame/buffer descriptors. */
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struct descriptor { /* A generic descriptor. */
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u16 status;
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u16 command;
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u32 link; /* struct descriptor * */
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unsigned char params[0];
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};
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#define CONFIG_SYS_CMD_EL 0x8000
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#define CONFIG_SYS_CMD_SUSPEND 0x4000
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#define CONFIG_SYS_CMD_INT 0x2000
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#define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */
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#define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */
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#define CONFIG_SYS_STATUS_C 0x8000
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#define CONFIG_SYS_STATUS_OK 0x2000
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/* Misc. */
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#define NUM_RX_DESC PKTBUFSRX
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#define NUM_TX_DESC 1 /* Number of TX descriptors */
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#define TOUT_LOOP 1000000
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/*
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* The parameters for a CmdConfigure operation.
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* There are so many options that it would be difficult to document
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* each bit. We mostly use the default or recommended settings.
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*/
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static const char i82558_config_cmd[] = {
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22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */
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0, 0x2E, 0, 0x60, 0x08, 0x88,
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0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */
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0x31, 0x05,
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};
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struct eepro100_priv {
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/* RX descriptor ring */
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struct eepro100_rxfd rx_ring[NUM_RX_DESC];
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/* TX descriptor ring */
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struct eepro100_txfd tx_ring[NUM_TX_DESC];
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/* RX descriptor ring pointer */
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int rx_next;
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u16 rx_stat;
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/* TX descriptor ring pointer */
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int tx_next;
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int tx_threshold;
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#ifdef CONFIG_DM_ETH
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struct udevice *devno;
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#else
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struct eth_device dev;
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pci_dev_t devno;
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#endif
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char *name;
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void __iomem *iobase;
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u8 *enetaddr;
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};
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#if defined(CONFIG_DM_ETH)
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#define bus_to_phys(dev, a) dm_pci_mem_to_phys((dev), (a))
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#define phys_to_bus(dev, a) dm_pci_phys_to_mem((dev), (a))
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#elif defined(CONFIG_E500)
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#define bus_to_phys(dev, a) (a)
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#define phys_to_bus(dev, a) (a)
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#else
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#define bus_to_phys(dev, a) pci_mem_to_phys((dev), (a))
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#define phys_to_bus(dev, a) pci_phys_to_mem((dev), (a))
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#endif
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static int INW(struct eepro100_priv *priv, u_long addr)
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{
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return le16_to_cpu(readw(addr + priv->iobase));
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}
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static void OUTW(struct eepro100_priv *priv, int command, u_long addr)
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{
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writew(cpu_to_le16(command), addr + priv->iobase);
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}
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static void OUTL(struct eepro100_priv *priv, int command, u_long addr)
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{
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writel(cpu_to_le32(command), addr + priv->iobase);
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}
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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static int INL(struct eepro100_priv *priv, u_long addr)
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{
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return le32_to_cpu(readl(addr + priv->iobase));
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}
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static int get_phyreg(struct eepro100_priv *priv, unsigned char addr,
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unsigned char reg, unsigned short *value)
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{
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int timeout = 50;
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int cmd;
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/* read requested data */
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cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
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OUTL(priv, cmd, SCB_CTRL_MDI);
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do {
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udelay(1000);
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cmd = INL(priv, SCB_CTRL_MDI);
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} while (!(cmd & (1 << 28)) && (--timeout));
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if (timeout == 0)
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return -1;
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*value = (unsigned short)(cmd & 0xffff);
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return 0;
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}
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static int set_phyreg(struct eepro100_priv *priv, unsigned char addr,
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unsigned char reg, unsigned short value)
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{
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int timeout = 50;
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int cmd;
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/* write requested data */
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cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
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OUTL(priv, cmd | value, SCB_CTRL_MDI);
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while (!(INL(priv, SCB_CTRL_MDI) & (1 << 28)) && (--timeout))
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udelay(1000);
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if (timeout == 0)
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return -1;
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return 0;
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}
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/*
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* Check if given phyaddr is valid, i.e. there is a PHY connected.
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* Do this by checking model value field from ID2 register.
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*/
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static int verify_phyaddr(struct eepro100_priv *priv, unsigned char addr)
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{
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unsigned short value, model;
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int ret;
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/* read id2 register */
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ret = get_phyreg(priv, addr, MII_PHYSID2, &value);
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if (ret) {
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printf("%s: mii read timeout!\n", priv->name);
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return ret;
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}
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/* get model */
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model = (value >> 4) & 0x003f;
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if (!model) {
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printf("%s: no PHY at address %d\n", priv->name, addr);
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return -EINVAL;
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}
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return 0;
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}
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static int eepro100_miiphy_read(struct mii_dev *bus, int addr, int devad,
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int reg)
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{
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struct eepro100_priv *priv = bus->priv;
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unsigned short value = 0;
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int ret;
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ret = verify_phyaddr(priv, addr);
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if (ret)
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return ret;
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ret = get_phyreg(priv, addr, reg, &value);
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if (ret) {
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printf("%s: mii read timeout!\n", bus->name);
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return ret;
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}
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return value;
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}
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static int eepro100_miiphy_write(struct mii_dev *bus, int addr, int devad,
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int reg, u16 value)
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{
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struct eepro100_priv *priv = bus->priv;
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int ret;
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ret = verify_phyaddr(priv, addr);
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if (ret)
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return ret;
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ret = set_phyreg(priv, addr, reg, value);
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if (ret) {
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printf("%s: mii write timeout!\n", bus->name);
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return ret;
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}
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return 0;
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}
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#endif
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static void init_rx_ring(struct eepro100_priv *priv)
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{
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struct eepro100_rxfd *rx_ring = priv->rx_ring;
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int i;
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for (i = 0; i < NUM_RX_DESC; i++) {
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rx_ring[i].status = 0;
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rx_ring[i].control = (i == NUM_RX_DESC - 1) ?
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cpu_to_le16 (RFD_CONTROL_S) : 0;
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rx_ring[i].link =
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cpu_to_le32(phys_to_bus(priv->devno,
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(u32)&rx_ring[(i + 1) %
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NUM_RX_DESC]));
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rx_ring[i].rx_buf_addr = 0xffffffff;
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rx_ring[i].count = cpu_to_le32(PKTSIZE_ALIGN << 16);
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}
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flush_dcache_range((unsigned long)rx_ring,
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(unsigned long)rx_ring +
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(sizeof(*rx_ring) * NUM_RX_DESC));
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priv->rx_next = 0;
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}
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static void purge_tx_ring(struct eepro100_priv *priv)
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{
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struct eepro100_txfd *tx_ring = priv->tx_ring;
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priv->tx_next = 0;
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priv->tx_threshold = 0x01208000;
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memset(tx_ring, 0, sizeof(*tx_ring) * NUM_TX_DESC);
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flush_dcache_range((unsigned long)tx_ring,
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(unsigned long)tx_ring +
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(sizeof(*tx_ring) * NUM_TX_DESC));
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}
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/* Wait for the chip get the command. */
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static int wait_for_eepro100(struct eepro100_priv *priv)
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{
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int i;
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for (i = 0; INW(priv, SCB_CMD) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
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if (i >= TOUT_LOOP)
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return 0;
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}
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return 1;
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}
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static int eepro100_txcmd_send(struct eepro100_priv *priv,
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struct eepro100_txfd *desc)
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{
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u16 rstat;
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int i = 0;
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flush_dcache_range((unsigned long)desc,
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(unsigned long)desc + sizeof(*desc));
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if (!wait_for_eepro100(priv))
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return -ETIMEDOUT;
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OUTL(priv, phys_to_bus(priv->devno, (u32)desc), SCB_POINTER);
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OUTW(priv, SCB_M | CU_START, SCB_CMD);
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while (true) {
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invalidate_dcache_range((unsigned long)desc,
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(unsigned long)desc + sizeof(*desc));
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rstat = le16_to_cpu(desc->status);
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if (rstat & CONFIG_SYS_STATUS_C)
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break;
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if (i++ >= TOUT_LOOP) {
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printf("%s: Tx error buffer not ready\n", priv->name);
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return -EINVAL;
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}
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}
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invalidate_dcache_range((unsigned long)desc,
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(unsigned long)desc + sizeof(*desc));
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rstat = le16_to_cpu(desc->status);
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if (!(rstat & CONFIG_SYS_STATUS_OK)) {
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printf("TX error status = 0x%08X\n", rstat);
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return -EIO;
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}
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return 0;
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}
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/* SROM Read. */
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static int read_eeprom(struct eepro100_priv *priv, int location, int addr_len)
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{
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unsigned short retval = 0;
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int read_cmd = location | EE_READ_CMD(addr_len);
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int i;
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OUTW(priv, EE_ENB & ~EE_CS, SCB_EEPROM);
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OUTW(priv, EE_ENB, SCB_EEPROM);
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/* Shift the read command bits out. */
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for (i = 12; i >= 0; i--) {
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short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
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OUTW(priv, EE_ENB | dataval, SCB_EEPROM);
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udelay(1);
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OUTW(priv, EE_ENB | dataval | EE_SHIFT_CLK, SCB_EEPROM);
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udelay(1);
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}
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OUTW(priv, EE_ENB, SCB_EEPROM);
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for (i = 15; i >= 0; i--) {
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OUTW(priv, EE_ENB | EE_SHIFT_CLK, SCB_EEPROM);
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udelay(1);
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retval = (retval << 1) |
|
|
!!(INW(priv, SCB_EEPROM) & EE_DATA_READ);
|
|
OUTW(priv, EE_ENB, SCB_EEPROM);
|
|
udelay(1);
|
|
}
|
|
|
|
/* Terminate the EEPROM access. */
|
|
OUTW(priv, EE_ENB & ~EE_CS, SCB_EEPROM);
|
|
return retval;
|
|
}
|
|
|
|
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
|
|
static int eepro100_initialize_mii(struct eepro100_priv *priv)
|
|
{
|
|
/* register mii command access routines */
|
|
struct mii_dev *mdiodev;
|
|
int ret;
|
|
|
|
mdiodev = mdio_alloc();
|
|
if (!mdiodev)
|
|
return -ENOMEM;
|
|
|
|
strncpy(mdiodev->name, priv->name, MDIO_NAME_LEN);
|
|
mdiodev->read = eepro100_miiphy_read;
|
|
mdiodev->write = eepro100_miiphy_write;
|
|
mdiodev->priv = priv;
|
|
|
|
ret = mdio_register(mdiodev);
|
|
if (ret < 0) {
|
|
mdio_free(mdiodev);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
static int eepro100_initialize_mii(struct eepro100_priv *priv)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static struct pci_device_id supported[] = {
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER) },
|
|
{ }
|
|
};
|
|
|
|
static void eepro100_get_hwaddr(struct eepro100_priv *priv)
|
|
{
|
|
u16 sum = 0;
|
|
int i, j;
|
|
int addr_len = read_eeprom(priv, 0, 6) == 0xffff ? 8 : 6;
|
|
|
|
for (j = 0, i = 0; i < 0x40; i++) {
|
|
u16 value = read_eeprom(priv, i, addr_len);
|
|
|
|
sum += value;
|
|
if (i < 3) {
|
|
priv->enetaddr[j++] = value;
|
|
priv->enetaddr[j++] = value >> 8;
|
|
}
|
|
}
|
|
|
|
if (sum != 0xBABA) {
|
|
memset(priv->enetaddr, 0, ETH_ALEN);
|
|
debug("%s: Invalid EEPROM checksum %#4.4x, check settings before activating this device!\n",
|
|
priv->name, sum);
|
|
}
|
|
}
|
|
|
|
static int eepro100_init_common(struct eepro100_priv *priv)
|
|
{
|
|
struct eepro100_rxfd *rx_ring = priv->rx_ring;
|
|
struct eepro100_txfd *tx_ring = priv->tx_ring;
|
|
struct eepro100_txfd *ias_cmd, *cfg_cmd;
|
|
int ret, status = -1;
|
|
int tx_cur;
|
|
|
|
/* Reset the ethernet controller */
|
|
OUTL(priv, I82559_SELECTIVE_RESET, SCB_PORT);
|
|
udelay(20);
|
|
|
|
OUTL(priv, I82559_RESET, SCB_PORT);
|
|
udelay(20);
|
|
|
|
if (!wait_for_eepro100(priv)) {
|
|
printf("Error: Can not reset ethernet controller.\n");
|
|
goto done;
|
|
}
|
|
OUTL(priv, 0, SCB_POINTER);
|
|
OUTW(priv, SCB_M | RUC_ADDR_LOAD, SCB_CMD);
|
|
|
|
if (!wait_for_eepro100(priv)) {
|
|
printf("Error: Can not reset ethernet controller.\n");
|
|
goto done;
|
|
}
|
|
OUTL(priv, 0, SCB_POINTER);
|
|
OUTW(priv, SCB_M | CU_ADDR_LOAD, SCB_CMD);
|
|
|
|
/* Initialize Rx and Tx rings. */
|
|
init_rx_ring(priv);
|
|
purge_tx_ring(priv);
|
|
|
|
/* Tell the adapter where the RX ring is located. */
|
|
if (!wait_for_eepro100(priv)) {
|
|
printf("Error: Can not reset ethernet controller.\n");
|
|
goto done;
|
|
}
|
|
|
|
/* RX ring cache was already flushed in init_rx_ring() */
|
|
OUTL(priv, phys_to_bus(priv->devno, (u32)&rx_ring[priv->rx_next]),
|
|
SCB_POINTER);
|
|
OUTW(priv, SCB_M | RUC_START, SCB_CMD);
|
|
|
|
/* Send the Configure frame */
|
|
tx_cur = priv->tx_next;
|
|
priv->tx_next = ((priv->tx_next + 1) % NUM_TX_DESC);
|
|
|
|
cfg_cmd = &tx_ring[tx_cur];
|
|
cfg_cmd->command = cpu_to_le16(CONFIG_SYS_CMD_SUSPEND |
|
|
CONFIG_SYS_CMD_CONFIGURE);
|
|
cfg_cmd->status = 0;
|
|
cfg_cmd->link = cpu_to_le32(phys_to_bus(priv->devno,
|
|
(u32)&tx_ring[priv->tx_next]));
|
|
|
|
memcpy(((struct descriptor *)cfg_cmd)->params, i82558_config_cmd,
|
|
sizeof(i82558_config_cmd));
|
|
|
|
ret = eepro100_txcmd_send(priv, cfg_cmd);
|
|
if (ret) {
|
|
if (ret == -ETIMEDOUT)
|
|
printf("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
|
|
goto done;
|
|
}
|
|
|
|
/* Send the Individual Address Setup frame */
|
|
tx_cur = priv->tx_next;
|
|
priv->tx_next = ((priv->tx_next + 1) % NUM_TX_DESC);
|
|
|
|
ias_cmd = &tx_ring[tx_cur];
|
|
ias_cmd->command = cpu_to_le16(CONFIG_SYS_CMD_SUSPEND |
|
|
CONFIG_SYS_CMD_IAS);
|
|
ias_cmd->status = 0;
|
|
ias_cmd->link = cpu_to_le32(phys_to_bus(priv->devno,
|
|
(u32)&tx_ring[priv->tx_next]));
|
|
|
|
memcpy(((struct descriptor *)ias_cmd)->params, priv->enetaddr, 6);
|
|
|
|
ret = eepro100_txcmd_send(priv, ias_cmd);
|
|
if (ret) {
|
|
if (ret == -ETIMEDOUT)
|
|
printf("Error: Can not reset ethernet controller.\n");
|
|
goto done;
|
|
}
|
|
|
|
status = 0;
|
|
|
|
done:
|
|
return status;
|
|
}
|
|
|
|
static int eepro100_send_common(struct eepro100_priv *priv,
|
|
void *packet, int length)
|
|
{
|
|
struct eepro100_txfd *tx_ring = priv->tx_ring;
|
|
struct eepro100_txfd *desc;
|
|
int ret, status = -1;
|
|
int tx_cur;
|
|
|
|
if (length <= 0) {
|
|
printf("%s: bad packet size: %d\n", priv->name, length);
|
|
goto done;
|
|
}
|
|
|
|
tx_cur = priv->tx_next;
|
|
priv->tx_next = (priv->tx_next + 1) % NUM_TX_DESC;
|
|
|
|
desc = &tx_ring[tx_cur];
|
|
desc->command = cpu_to_le16(TXCB_CMD_TRANSMIT | TXCB_CMD_SF |
|
|
TXCB_CMD_S | TXCB_CMD_EL);
|
|
desc->status = 0;
|
|
desc->count = cpu_to_le32(priv->tx_threshold);
|
|
desc->link = cpu_to_le32(phys_to_bus(priv->devno,
|
|
(u32)&tx_ring[priv->tx_next]));
|
|
desc->tx_desc_addr = cpu_to_le32(phys_to_bus(priv->devno,
|
|
(u32)&desc->tx_buf_addr0));
|
|
desc->tx_buf_addr0 = cpu_to_le32(phys_to_bus(priv->devno,
|
|
(u_long)packet));
|
|
desc->tx_buf_size0 = cpu_to_le32(length);
|
|
|
|
ret = eepro100_txcmd_send(priv, &tx_ring[tx_cur]);
|
|
if (ret) {
|
|
if (ret == -ETIMEDOUT)
|
|
printf("%s: Tx error ethernet controller not ready.\n",
|
|
priv->name);
|
|
goto done;
|
|
}
|
|
|
|
status = length;
|
|
|
|
done:
|
|
return status;
|
|
}
|
|
|
|
static int eepro100_recv_common(struct eepro100_priv *priv, uchar **packetp)
|
|
{
|
|
struct eepro100_rxfd *rx_ring = priv->rx_ring;
|
|
struct eepro100_rxfd *desc;
|
|
int length;
|
|
u16 status;
|
|
|
|
priv->rx_stat = INW(priv, SCB_STATUS);
|
|
OUTW(priv, priv->rx_stat & SCB_STATUS_RNR, SCB_STATUS);
|
|
|
|
desc = &rx_ring[priv->rx_next];
|
|
invalidate_dcache_range((unsigned long)desc,
|
|
(unsigned long)desc + sizeof(*desc));
|
|
status = le16_to_cpu(desc->status);
|
|
|
|
if (!(status & RFD_STATUS_C))
|
|
return 0;
|
|
|
|
/* Valid frame status. */
|
|
if (status & RFD_STATUS_OK) {
|
|
/* A valid frame received. */
|
|
length = le32_to_cpu(desc->count) & 0x3fff;
|
|
/* Pass the packet up to the protocol layers. */
|
|
*packetp = desc->data;
|
|
return length;
|
|
}
|
|
|
|
/* There was an error. */
|
|
printf("RX error status = 0x%08X\n", status);
|
|
return -EINVAL;
|
|
}
|
|
|
|
static void eepro100_free_pkt_common(struct eepro100_priv *priv)
|
|
{
|
|
struct eepro100_rxfd *rx_ring = priv->rx_ring;
|
|
struct eepro100_rxfd *desc;
|
|
int rx_prev;
|
|
|
|
desc = &rx_ring[priv->rx_next];
|
|
|
|
desc->control = cpu_to_le16(RFD_CONTROL_S);
|
|
desc->status = 0;
|
|
desc->count = cpu_to_le32(PKTSIZE_ALIGN << 16);
|
|
flush_dcache_range((unsigned long)desc,
|
|
(unsigned long)desc + sizeof(*desc));
|
|
|
|
rx_prev = (priv->rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
|
|
desc = &rx_ring[rx_prev];
|
|
desc->control = 0;
|
|
flush_dcache_range((unsigned long)desc,
|
|
(unsigned long)desc + sizeof(*desc));
|
|
|
|
/* Update entry information. */
|
|
priv->rx_next = (priv->rx_next + 1) % NUM_RX_DESC;
|
|
|
|
if (!(priv->rx_stat & SCB_STATUS_RNR))
|
|
return;
|
|
|
|
printf("%s: Receiver is not ready, restart it !\n", priv->name);
|
|
|
|
/* Reinitialize Rx ring. */
|
|
init_rx_ring(priv);
|
|
|
|
if (!wait_for_eepro100(priv)) {
|
|
printf("Error: Can not restart ethernet controller.\n");
|
|
return;
|
|
}
|
|
|
|
/* RX ring cache was already flushed in init_rx_ring() */
|
|
OUTL(priv, phys_to_bus(priv->devno, (u32)&rx_ring[priv->rx_next]),
|
|
SCB_POINTER);
|
|
OUTW(priv, SCB_M | RUC_START, SCB_CMD);
|
|
}
|
|
|
|
static void eepro100_halt_common(struct eepro100_priv *priv)
|
|
{
|
|
/* Reset the ethernet controller */
|
|
OUTL(priv, I82559_SELECTIVE_RESET, SCB_PORT);
|
|
udelay(20);
|
|
|
|
OUTL(priv, I82559_RESET, SCB_PORT);
|
|
udelay(20);
|
|
|
|
if (!wait_for_eepro100(priv)) {
|
|
printf("Error: Can not reset ethernet controller.\n");
|
|
goto done;
|
|
}
|
|
OUTL(priv, 0, SCB_POINTER);
|
|
OUTW(priv, SCB_M | RUC_ADDR_LOAD, SCB_CMD);
|
|
|
|
if (!wait_for_eepro100(priv)) {
|
|
printf("Error: Can not reset ethernet controller.\n");
|
|
goto done;
|
|
}
|
|
OUTL(priv, 0, SCB_POINTER);
|
|
OUTW(priv, SCB_M | CU_ADDR_LOAD, SCB_CMD);
|
|
|
|
done:
|
|
return;
|
|
}
|
|
|
|
#ifndef CONFIG_DM_ETH
|
|
static int eepro100_init(struct eth_device *dev, struct bd_info *bis)
|
|
{
|
|
struct eepro100_priv *priv =
|
|
container_of(dev, struct eepro100_priv, dev);
|
|
|
|
return eepro100_init_common(priv);
|
|
}
|
|
|
|
static void eepro100_halt(struct eth_device *dev)
|
|
{
|
|
struct eepro100_priv *priv =
|
|
container_of(dev, struct eepro100_priv, dev);
|
|
|
|
eepro100_halt_common(priv);
|
|
}
|
|
|
|
static int eepro100_send(struct eth_device *dev, void *packet, int length)
|
|
{
|
|
struct eepro100_priv *priv =
|
|
container_of(dev, struct eepro100_priv, dev);
|
|
|
|
return eepro100_send_common(priv, packet, length);
|
|
}
|
|
|
|
static int eepro100_recv(struct eth_device *dev)
|
|
{
|
|
struct eepro100_priv *priv =
|
|
container_of(dev, struct eepro100_priv, dev);
|
|
uchar *packet;
|
|
int ret;
|
|
|
|
ret = eepro100_recv_common(priv, &packet);
|
|
if (ret > 0)
|
|
net_process_received_packet(packet, ret);
|
|
if (ret)
|
|
eepro100_free_pkt_common(priv);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int eepro100_initialize(struct bd_info *bis)
|
|
{
|
|
struct eepro100_priv *priv;
|
|
struct eth_device *dev;
|
|
int card_number = 0;
|
|
u32 iobase, status;
|
|
pci_dev_t devno;
|
|
int idx = 0;
|
|
int ret;
|
|
|
|
while (1) {
|
|
/* Find PCI device */
|
|
devno = pci_find_devices(supported, idx++);
|
|
if (devno < 0)
|
|
break;
|
|
|
|
pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
|
|
iobase &= ~0xf;
|
|
|
|
debug("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
|
|
iobase);
|
|
|
|
pci_write_config_dword(devno, PCI_COMMAND,
|
|
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
|
|
|
/* Check if I/O accesses and Bus Mastering are enabled. */
|
|
pci_read_config_dword(devno, PCI_COMMAND, &status);
|
|
if (!(status & PCI_COMMAND_MEMORY)) {
|
|
printf("Error: Can not enable MEM access.\n");
|
|
continue;
|
|
}
|
|
|
|
if (!(status & PCI_COMMAND_MASTER)) {
|
|
printf("Error: Can not enable Bus Mastering.\n");
|
|
continue;
|
|
}
|
|
|
|
priv = calloc(1, sizeof(*priv));
|
|
if (!priv) {
|
|
printf("eepro100: Can not allocate memory\n");
|
|
break;
|
|
}
|
|
dev = &priv->dev;
|
|
|
|
sprintf(dev->name, "i82559#%d", card_number);
|
|
priv->name = dev->name;
|
|
/* this have to come before bus_to_phys() */
|
|
priv->devno = devno;
|
|
priv->iobase = (void __iomem *)bus_to_phys(devno, iobase);
|
|
priv->enetaddr = dev->enetaddr;
|
|
|
|
dev->init = eepro100_init;
|
|
dev->halt = eepro100_halt;
|
|
dev->send = eepro100_send;
|
|
dev->recv = eepro100_recv;
|
|
|
|
eth_register(dev);
|
|
|
|
ret = eepro100_initialize_mii(priv);
|
|
if (ret) {
|
|
eth_unregister(dev);
|
|
free(priv);
|
|
return ret;
|
|
}
|
|
|
|
card_number++;
|
|
|
|
/* Set the latency timer for value. */
|
|
pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
|
|
|
|
udelay(10 * 1000);
|
|
|
|
eepro100_get_hwaddr(priv);
|
|
}
|
|
|
|
return card_number;
|
|
}
|
|
|
|
#else /* DM_ETH */
|
|
static int eepro100_start(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *plat = dev_get_plat(dev);
|
|
struct eepro100_priv *priv = dev_get_priv(dev);
|
|
|
|
memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
|
|
|
|
return eepro100_init_common(priv);
|
|
}
|
|
|
|
static void eepro100_stop(struct udevice *dev)
|
|
{
|
|
struct eepro100_priv *priv = dev_get_priv(dev);
|
|
|
|
eepro100_halt_common(priv);
|
|
}
|
|
|
|
static int eepro100_send(struct udevice *dev, void *packet, int length)
|
|
{
|
|
struct eepro100_priv *priv = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
ret = eepro100_send_common(priv, packet, length);
|
|
|
|
return ret ? 0 : -ETIMEDOUT;
|
|
}
|
|
|
|
static int eepro100_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
{
|
|
struct eepro100_priv *priv = dev_get_priv(dev);
|
|
|
|
return eepro100_recv_common(priv, packetp);
|
|
}
|
|
|
|
static int eepro100_free_pkt(struct udevice *dev, uchar *packet, int length)
|
|
{
|
|
struct eepro100_priv *priv = dev_get_priv(dev);
|
|
|
|
eepro100_free_pkt_common(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int eepro100_read_rom_hwaddr(struct udevice *dev)
|
|
{
|
|
struct eepro100_priv *priv = dev_get_priv(dev);
|
|
|
|
eepro100_get_hwaddr(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int eepro100_bind(struct udevice *dev)
|
|
{
|
|
static int card_number;
|
|
char name[16];
|
|
|
|
sprintf(name, "eepro100#%u", card_number++);
|
|
|
|
return device_set_name(dev, name);
|
|
}
|
|
|
|
static int eepro100_probe(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *plat = dev_get_plat(dev);
|
|
struct eepro100_priv *priv = dev_get_priv(dev);
|
|
u16 command, status;
|
|
u32 iobase;
|
|
int ret;
|
|
|
|
dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
|
|
iobase &= ~0xf;
|
|
|
|
debug("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n", iobase);
|
|
|
|
priv->devno = dev;
|
|
priv->enetaddr = plat->enetaddr;
|
|
priv->iobase = (void __iomem *)bus_to_phys(dev, iobase);
|
|
|
|
command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
|
|
dm_pci_write_config16(dev, PCI_COMMAND, command);
|
|
dm_pci_read_config16(dev, PCI_COMMAND, &status);
|
|
if ((status & command) != command) {
|
|
printf("eepro100: Couldn't enable IO access or Bus Mastering\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = eepro100_initialize_mii(priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops eepro100_ops = {
|
|
.start = eepro100_start,
|
|
.send = eepro100_send,
|
|
.recv = eepro100_recv,
|
|
.stop = eepro100_stop,
|
|
.free_pkt = eepro100_free_pkt,
|
|
.read_rom_hwaddr = eepro100_read_rom_hwaddr,
|
|
};
|
|
|
|
U_BOOT_DRIVER(eth_eepro100) = {
|
|
.name = "eth_eepro100",
|
|
.id = UCLASS_ETH,
|
|
.bind = eepro100_bind,
|
|
.probe = eepro100_probe,
|
|
.ops = &eepro100_ops,
|
|
.priv_auto = sizeof(struct eepro100_priv),
|
|
.plat_auto = sizeof(struct eth_pdata),
|
|
};
|
|
|
|
U_BOOT_PCI_DEVICE(eth_eepro100, supported);
|
|
#endif
|