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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
246 lines
5.3 KiB
C
246 lines
5.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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*
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* Author: Scott Wood <scottwood@freescale.com>
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* Dave Liu <daveliu@freescale.com>
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*/
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#include <common.h>
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#include <hwconfig.h>
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#include <i2c.h>
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#include <linux/libfdt.h>
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#include <fdt_support.h>
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#include <pci.h>
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#include <mpc83xx.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <ns16550.h>
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#include <nand.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
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gd->flags |= GD_FLG_SILENT;
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return 0;
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}
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#ifndef CONFIG_NAND_SPL
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static u8 read_board_info(void)
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{
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u8 val8;
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i2c_set_bus_num(0);
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if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
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return val8;
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else
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return 0;
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}
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int checkboard(void)
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{
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static const char * const rev_str[] = {
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"0.0",
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"0.1",
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"1.0",
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"1.1",
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"<unknown>",
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};
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u8 info;
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int i;
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info = read_board_info();
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i = (!info) ? 4: info & 0x03;
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printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
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return 0;
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}
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static struct pci_region pci_regions[] = {
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{
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bus_start: CONFIG_SYS_PCI_MEM_BASE,
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phys_start: CONFIG_SYS_PCI_MEM_PHYS,
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size: CONFIG_SYS_PCI_MEM_SIZE,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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bus_start: CONFIG_SYS_PCI_MMIO_BASE,
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phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
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size: CONFIG_SYS_PCI_MMIO_SIZE,
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flags: PCI_REGION_MEM
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},
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{
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bus_start: CONFIG_SYS_PCI_IO_BASE,
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phys_start: CONFIG_SYS_PCI_IO_PHYS,
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size: CONFIG_SYS_PCI_IO_SIZE,
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flags: PCI_REGION_IO
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}
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};
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static struct pci_region pcie_regions_0[] = {
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{
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.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
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.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
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.size = CONFIG_SYS_PCIE1_MEM_SIZE,
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.flags = PCI_REGION_MEM,
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},
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{
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.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
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.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
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.size = CONFIG_SYS_PCIE1_IO_SIZE,
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.flags = PCI_REGION_IO,
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},
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};
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static struct pci_region pcie_regions_1[] = {
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{
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.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
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.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
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.size = CONFIG_SYS_PCIE2_MEM_SIZE,
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.flags = PCI_REGION_MEM,
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},
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{
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.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
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.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
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.size = CONFIG_SYS_PCIE2_IO_SIZE,
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.flags = PCI_REGION_IO,
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},
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};
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void pci_init_board(void)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile sysconf83xx_t *sysconf = &immr->sysconf;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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volatile law83xx_t *pcie_law = sysconf->pcielaw;
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struct pci_region *reg[] = { pci_regions };
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struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
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/* Enable all 3 PCI_CLK_OUTPUTs. */
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clk->occr |= 0xe0000000;
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/*
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* Configure PCI Local Access Windows
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*/
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pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
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pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
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mpc83xx_pci_init(1, reg);
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/* Configure the clock for PCIE controller */
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clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
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SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
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/* Deassert the resets in the control register */
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out_be32(&sysconf->pecr1, 0xE0008000);
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out_be32(&sysconf->pecr2, 0xE0008000);
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udelay(2000);
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/* Configure PCI Express Local Access Windows */
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out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
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out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
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out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
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out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
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mpc83xx_pcie_init(2, pcie_reg);
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void fdt_tsec1_fixup(void *fdt, bd_t *bd)
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{
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const char disabled[] = "disabled";
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const char *path;
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int ret;
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if (hwconfig_arg_cmp("board_type", "tsec1")) {
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return;
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} else if (!hwconfig_arg_cmp("board_type", "ulpi")) {
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printf("NOTICE: No or unknown board_type hwconfig specified.\n"
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" Assuming board with TSEC1.\n");
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return;
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}
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ret = fdt_path_offset(fdt, "/aliases");
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if (ret < 0) {
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printf("WARNING: can't find /aliases node\n");
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return;
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}
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path = fdt_getprop(fdt, ret, "ethernet0", NULL);
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if (!path) {
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printf("WARNING: can't find ethernet0 alias\n");
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return;
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}
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do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
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}
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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fsl_fdt_fixup_dr_usb(blob, bd);
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fdt_tsec1_fixup(blob, bd);
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return 0;
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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cpu_eth_init(bis); /* Initialize TSECs first */
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return pci_eth_init(bis);
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}
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#else /* CONFIG_NAND_SPL */
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int checkboard(void)
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{
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puts("Board: Freescale MPC8315ERDB\n");
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return 0;
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}
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void board_init_f(ulong bootflag)
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{
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board_early_init_f();
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NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
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CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
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puts("NAND boot... ");
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timer_init();
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dram_init();
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relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
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CONFIG_SYS_NAND_U_BOOT_RELOC);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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nand_boot();
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}
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void putc(char c)
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{
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if (gd->flags & GD_FLG_SILENT)
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return;
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if (c == '\n')
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NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
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NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
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}
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#endif /* CONFIG_NAND_SPL */
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