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https://github.com/brain-hackers/u-boot-brain
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0405092bd2
Specify standard padding for payload to 68KB. This is derived from the maximum header size plus maximum SPL size. It matches the already defined offset for SD/eMMC devices (69KB) too. This allows to use the u-boot-with-spl.imx build target to generate a directly flashable image which can be flashed using: dd if=u-boot-with-spl.imx of=/dev/mmcblk0 bs=512 skip=2 While the patch has been created with SD/eMMC in mind, this also works with other boot media. The board file needs to configure the media specific (absolute) payload offset accordingly. Especially the IVT offset is boot media specific and can be retrieved from the reference manual (Table 8-25. Image Vector Table Offset and Initial Load Region Size). For NAND boot a define like this should do the job: #define CONFIG_SYS_NAND_U_BOOT_OFFS (SPL_PAD_TO + 0x400) Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
79 lines
2.6 KiB
C
79 lines
2.6 KiB
C
/*
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* Copyright (C) 2014 Gateworks Corporation
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* Author: Tim Harvey <tharvey@gateworks.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __IMX6_SPL_CONFIG_H
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#define __IMX6_SPL_CONFIG_H
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#ifdef CONFIG_SPL
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#define CONFIG_SPL_FRAMEWORK
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/*
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* see Figure 8-3 in IMX6DQ/IMX6SDL Reference manuals:
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* - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF
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* - IMX6DQ has 2x IRAM of IMX6SDL but we intend to support IMX6SDL as well
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* - BOOT ROM stack is at 0x0091FFB8
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* - if icache/dcache is enabled (eFuse/strapping controlled) then the
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* IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to
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* fit between 0x00907000 and 0x00918000.
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* - Additionally the BOOT ROM loads what they consider the firmware image
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* which consists of a 4K header in front of us that contains the IVT, DCD
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* and some padding thus 'our' max size is really 0x00908000 - 0x00918000
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* or 64KB
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*/
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#define CONFIG_SYS_THUMB_BUILD
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#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
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#define CONFIG_SPL_TEXT_BASE 0x00908000
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#define CONFIG_SPL_MAX_SIZE 0x10000
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#define CONFIG_SPL_STACK 0x0091FFB8
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/*
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* Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the
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* SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
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* boot media (given that boot media specific offset is configured properly).
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*/
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#define CONFIG_SPL_PAD_TO 0x11000
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/* NAND support */
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#if defined(CONFIG_SPL_NAND_SUPPORT)
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#define CONFIG_SPL_NAND_MXS
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#endif
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/* MMC support */
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#if defined(CONFIG_SPL_MMC_SUPPORT)
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */
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#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
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#endif
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/* SATA support */
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#if defined(CONFIG_SPL_SATA_SUPPORT)
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#define CONFIG_SPL_SATA_BOOT_DEVICE 0
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#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1
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#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
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#endif
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/* Define the payload for FAT/EXT support */
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#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
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#endif
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#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6SL)
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#define CONFIG_SPL_BSS_START_ADDR 0x88200000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
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#define CONFIG_SYS_SPL_MALLOC_START 0x88300000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
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#define CONFIG_SYS_TEXT_BASE 0x87800000
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#else
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#define CONFIG_SPL_BSS_START_ADDR 0x18200000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
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#define CONFIG_SYS_SPL_MALLOC_START 0x18300000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
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#define CONFIG_SYS_TEXT_BASE 0x17800000
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#endif
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#endif
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#endif
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