mirror of
https://github.com/brain-hackers/u-boot-brain
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98f705c9ce
There was for long time no activity in the 4xx area. We need to go further and convert to Kconfig, but it turned out, nobody is interested anymore in 4xx, so remove it. Signed-off-by: Heiko Schocher <hs@denx.de>
267 lines
9.4 KiB
C
267 lines
9.4 KiB
C
/*
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* Xilinx xps_ll_temac ethernet driver for u-boot
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*
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* SDMA sub-controller interface
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*
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* Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net>
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* Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2008 - 2011 PetaLogix
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*
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* Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver
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* Copyright (C) 2008 Nissin Systems Co.,Ltd.
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* March 2008 created
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* [0]: http://www.xilinx.com/support/documentation
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*
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* [S]: [0]/ip_documentation/xps_ll_temac.pdf
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* [A]: [0]/application_notes/xapp1041.pdf
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*/
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#ifndef _XILINX_LL_TEMAC_SDMA_
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#define _XILINX_LL_TEMAC_SDMA_
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#include <net.h>
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#include <asm/types.h>
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#include <asm/byteorder.h>
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#include <linux/compiler.h>
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#if !defined(__BIG_ENDIAN)
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# error LL_TEMAC requires big endianess
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#endif
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/*
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* DMA Buffer Descriptor for CDMAC
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*
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* Used for data connection from and to (Rx/Tx) the LocalLink (LL) TEMAC via
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* the Communications Direct Memory Access Controller (CDMAC) -- one for each.
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*
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* overview:
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* ftp://ftp.xilinx.com/pub/documentation/misc/mpmc_getting_started.pdf
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*
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* [1]: [0]/ip_documentation/mpmc.pdf
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* page 140, DMA Operation Descriptors
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*
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* [2]: [0]/user_guides/ug200.pdf
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* page 229, DMA Controller -- Descriptor Format
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*
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* [3]: [0]/ip_documentation/xps_ll_temac.pdf
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* page 72, Transmit LocalLink Frame Format
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* page 73, Receive LocalLink Frame Format
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*/
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struct cdmac_bd {
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struct cdmac_bd *next_p; /* Next Descriptor Pointer */
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u8 *phys_buf_p; /* Buffer Address */
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u32 buf_len; /* Buffer Length */
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union {
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u8 stctrl; /* Status/Control the DMA transfer */
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u32 app[5]; /* application specific data */
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} __packed __aligned(1) sca;
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};
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/* CDMAC Descriptor Status and Control (stctrl), [1] p140, [2] p230 */
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#define CDMAC_BD_STCTRL_ERROR (1 << 7)
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#define CDMAC_BD_STCTRL_IRQ_ON_END (1 << 6)
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#define CDMAC_BD_STCTRL_STOP_ON_END (1 << 5)
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#define CDMAC_BD_STCTRL_COMPLETED (1 << 4)
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#define CDMAC_BD_STCTRL_SOP (1 << 3)
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#define CDMAC_BD_STCTRL_EOP (1 << 2)
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#define CDMAC_BD_STCTRL_DMACHBUSY (1 << 1)
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/* CDMAC Descriptor APP0: Transmit LocalLink Footer Word 3, [3] p72 */
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#define CDMAC_BD_APP0_TXCSCNTRL (1 << 0)
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/* CDMAC Descriptor APP1: Transmit LocalLink Footer Word 4, [3] p73 */
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#define CDMAC_BD_APP1_TXCSBEGIN_POS 16
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#define CDMAC_BD_APP1_TXCSBEGIN_MASK (0xFFFF << CDMAC_BD_APP1_TXCSBEGIN_POS)
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#define CDMAC_BD_APP1_TXCSINSERT_POS 0
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#define CDMAC_BD_APP1_TXCSINSERT_MASK (0xFFFF << CDMAC_BD_APP1_TXCSINSERT_POS)
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/* CDMAC Descriptor APP2: Transmit LocalLink Footer Word 5, [3] p73 */
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#define CDMAC_BD_APP2_TXCSINIT_POS 0
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#define CDMAC_BD_APP2_TXCSINIT_MASK (0xFFFF << CDMAC_BD_APP2_TXCSINIT_POS)
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/* CDMAC Descriptor APP0: Receive LocalLink Footer Word 3, [3] p73 */
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#define CDMAC_BD_APP0_MADDRU_POS 0
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#define CDMAC_BD_APP0_MADDRU_MASK (0xFFFF << CDMAC_BD_APP0_MADDRU_POS)
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/* CDMAC Descriptor APP1: Receive LocalLink Footer Word 4, [3] p74 */
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#define CDMAC_BD_APP1_MADDRL_POS 0
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#define CDMAC_BD_APP1_MADDRL_MASK (~0UL << CDMAC_BD_APP1_MADDRL_POS)
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/* CDMAC Descriptor APP2: Receive LocalLink Footer Word 5, [3] p74 */
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#define CDMAC_BD_APP2_BCAST_FRAME (1 << 2)
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#define CDMAC_BD_APP2_IPC_MCAST_FRAME (1 << 1)
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#define CDMAC_BD_APP2_MAC_MCAST_FRAME (1 << 0)
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/* CDMAC Descriptor APP3: Receive LocalLink Footer Word 6, [3] p74 */
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#define CDMAC_BD_APP3_TLTPID_POS 16
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#define CDMAC_BD_APP3_TLTPID_MASK (0xFFFF << CDMAC_BD_APP3_TLTPID_POS)
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#define CDMAC_BD_APP3_RXCSRAW_POS 0
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#define CDMAC_BD_APP3_RXCSRAW_MASK (0xFFFF << CDMAC_BD_APP3_RXCSRAW_POS)
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/* CDMAC Descriptor APP4: Receive LocalLink Footer Word 7, [3] p74 */
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#define CDMAC_BD_APP4_VLANTAG_POS 16
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#define CDMAC_BD_APP4_VLANTAG_MASK (0xFFFF << CDMAC_BD_APP4_VLANTAG_POS)
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#define CDMAC_BD_APP4_RXBYTECNT_POS 0
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#define CDMAC_BD_APP4_RXBYTECNT_MASK (0x3FFF << CDMAC_BD_APP4_RXBYTECNT_POS)
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/*
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* SDMA Register Definition
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*
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* [0]: http://www.xilinx.com/support/documentation
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*
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* [1]: [0]/ip_documentation/mpmc.pdf
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* page 54, SDMA Register Summary
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* page 160, SDMA Registers
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*
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* [2]: [0]/user_guides/ug200.pdf
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* page 244, DMA Controller -- Programming Interface and Registers
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*/
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#define SDMA_CTRL_REGTYPE u32
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#define SDMA_CTRL_REGSIZE sizeof(SDMA_CTRL_REGTYPE)
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struct sdma_ctrl {
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/* Transmit Registers */
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SDMA_CTRL_REGTYPE tx_nxtdesc_ptr; /* TX Next Description Pointer */
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SDMA_CTRL_REGTYPE tx_curbuf_addr; /* TX Current Buffer Address */
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SDMA_CTRL_REGTYPE tx_curbuf_length; /* TX Current Buffer Length */
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SDMA_CTRL_REGTYPE tx_curdesc_ptr; /* TX Current Descriptor Pointer */
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SDMA_CTRL_REGTYPE tx_taildesc_ptr; /* TX Tail Descriptor Pointer */
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SDMA_CTRL_REGTYPE tx_chnl_ctrl; /* TX Channel Control */
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SDMA_CTRL_REGTYPE tx_irq_reg; /* TX Interrupt Register */
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SDMA_CTRL_REGTYPE tx_chnl_sts; /* TX Status Register */
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/* Receive Registers */
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SDMA_CTRL_REGTYPE rx_nxtdesc_ptr; /* RX Next Descriptor Pointer */
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SDMA_CTRL_REGTYPE rx_curbuf_addr; /* RX Current Buffer Address */
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SDMA_CTRL_REGTYPE rx_curbuf_length; /* RX Current Buffer Length */
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SDMA_CTRL_REGTYPE rx_curdesc_ptr; /* RX Current Descriptor Pointer */
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SDMA_CTRL_REGTYPE rx_taildesc_ptr; /* RX Tail Descriptor Pointer */
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SDMA_CTRL_REGTYPE rx_chnl_ctrl; /* RX Channel Control */
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SDMA_CTRL_REGTYPE rx_irq_reg; /* RX Interrupt Register */
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SDMA_CTRL_REGTYPE rx_chnl_sts; /* RX Status Register */
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/* Control Registers */
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SDMA_CTRL_REGTYPE dma_control_reg; /* DMA Control Register */
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};
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#define SDMA_CTRL_REGNUMS sizeof(struct sdma_ctrl)/SDMA_CTRL_REGSIZE
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/*
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* DMAC Register Index Enumeration
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*
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* [2]: http://www.xilinx.com/support/documentation/user_guides/ug200.pdf
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* page 244, DMA Controller -- Programming Interface and Registers
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*/
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enum dmac_ctrl {
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/* Transmit Registers */
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TX_NXTDESC_PTR = 0, /* TX Next Description Pointer */
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TX_CURBUF_ADDR, /* TX Current Buffer Address */
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TX_CURBUF_LENGTH, /* TX Current Buffer Length */
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TX_CURDESC_PTR, /* TX Current Descriptor Pointer */
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TX_TAILDESC_PTR, /* TX Tail Descriptor Pointer */
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TX_CHNL_CTRL, /* TX Channel Control */
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TX_IRQ_REG, /* TX Interrupt Register */
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TX_CHNL_STS, /* TX Status Register */
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/* Receive Registers */
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RX_NXTDESC_PTR, /* RX Next Descriptor Pointer */
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RX_CURBUF_ADDR, /* RX Current Buffer Address */
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RX_CURBUF_LENGTH, /* RX Current Buffer Length */
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RX_CURDESC_PTR, /* RX Current Descriptor Pointer */
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RX_TAILDESC_PTR, /* RX Tail Descriptor Pointer */
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RX_CHNL_CTRL, /* RX Channel Control */
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RX_IRQ_REG, /* RX Interrupt Register */
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RX_CHNL_STS, /* RX Status Register */
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/* Control Registers */
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DMA_CONTROL_REG /* DMA Control Register */
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};
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/* Rx/Tx Channel Control Register (*_chnl_ctrl), [1] p163, [2] p246/p252 */
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#define CHNL_CTRL_ITO_POS 24
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#define CHNL_CTRL_ITO_MASK (0xFF << CHNL_CTRL_ITO_POS)
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#define CHNL_CTRL_IC_POS 16
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#define CHNL_CTRL_IC_MASK (0xFF << CHNL_CTRL_IC_POS)
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#define CHNL_CTRL_MSBADDR_POS 12
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#define CHNL_CTRL_MSBADDR_MASK (0xF << CHNL_CTRL_MSBADDR_POS)
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#define CHNL_CTRL_AME (1 << 11)
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#define CHNL_CTRL_OBWC (1 << 10)
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#define CHNL_CTRL_IOE (1 << 9)
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#define CHNL_CTRL_LIC (1 << 8)
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#define CHNL_CTRL_IE (1 << 7)
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#define CHNL_CTRL_IEE (1 << 2)
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#define CHNL_CTRL_IDE (1 << 1)
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#define CHNL_CTRL_ICE (1 << 0)
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/* All interrupt enable bits */
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#define CHNL_CTRL_IRQ_MASK (CHNL_CTRL_IE | \
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CHNL_CTRL_IEE | \
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CHNL_CTRL_IDE | \
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CHNL_CTRL_ICE)
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/* Rx/Tx Interrupt Status Register (*_irq_reg), [1] p164, [2] p247/p253 */
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#define IRQ_REG_DTV_POS 24
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#define IRQ_REG_DTV_MASK (0xFF << IRQ_REG_DTV_POS)
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#define IRQ_REG_CCV_POS 16
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#define IRQ_REG_CCV_MASK (0xFF << IRQ_REG_CCV_POS)
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#define IRQ_REG_WRCQ_EMPTY (1 << 14)
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#define IRQ_REG_CIC_POS 10
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#define IRQ_REG_CIC_MASK (0xF << IRQ_REG_CIC_POS)
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#define IRQ_REG_DIC_POS 8
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#define IRQ_REG_DIC_MASK (3 << 8)
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#define IRQ_REG_PLB_RD_NMI (1 << 4)
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#define IRQ_REG_PLB_WR_NMI (1 << 3)
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#define IRQ_REG_EI (1 << 2)
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#define IRQ_REG_DI (1 << 1)
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#define IRQ_REG_CI (1 << 0)
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/* All interrupt bits */
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#define IRQ_REG_IRQ_MASK (IRQ_REG_PLB_RD_NMI | \
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IRQ_REG_PLB_WR_NMI | \
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IRQ_REG_EI | IRQ_REG_DI | IRQ_REG_CI)
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/* Rx/Tx Channel Status Register (*_chnl_sts), [1] p165, [2] p249/p255 */
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#define CHNL_STS_ERROR_TAIL (1 << 21)
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#define CHNL_STS_ERROR_CMP (1 << 20)
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#define CHNL_STS_ERROR_ADDR (1 << 19)
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#define CHNL_STS_ERROR_NXTP (1 << 18)
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#define CHNL_STS_ERROR_CURP (1 << 17)
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#define CHNL_STS_ERROR_BSYWR (1 << 16)
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#define CHNL_STS_ERROR (1 << 7)
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#define CHNL_STS_IOE (1 << 6)
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#define CHNL_STS_SOE (1 << 5)
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#define CHNL_STS_CMPLT (1 << 4)
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#define CHNL_STS_SOP (1 << 3)
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#define CHNL_STS_EOP (1 << 2)
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#define CHNL_STS_EBUSY (1 << 1)
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/* DMA Control Register (dma_control_reg), [1] p166, [2] p256 */
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#define DMA_CONTROL_PLBED (1 << 5)
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#define DMA_CONTROL_RXOCEID (1 << 4)
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#define DMA_CONTROL_TXOCEID (1 << 3)
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#define DMA_CONTROL_TPE (1 << 2)
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#define DMA_CONTROL_RESET (1 << 0)
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/* Xilinx Processor Local Bus (PLB) in/out accessors */
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unsigned ll_temac_xlplb_in32(phys_addr_t base);
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void ll_temac_xlplb_out32(phys_addr_t base, unsigned value);
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/* collect all register addresses for Xilinx PLB in/out accessors */
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void ll_temac_collect_xlplb_sdma_reg_addr(struct eth_device *dev);
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/* initialize both Rx/Tx buffer descriptors */
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int ll_temac_init_sdma(struct eth_device *dev);
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/* halt both Rx/Tx transfers */
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int ll_temac_halt_sdma(struct eth_device *dev);
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/* reset SDMA and IRQ, disable interrupts and errors */
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int ll_temac_reset_sdma(struct eth_device *dev);
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/* receive buffered data from SDMA (polling ISR) */
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int ll_temac_recv_sdma(struct eth_device *dev);
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/* send buffered data to SDMA */
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int ll_temac_send_sdma(struct eth_device *dev, void *packet, int length);
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#endif /* _XILINX_LL_TEMAC_SDMA_ */
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