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https://github.com/brain-hackers/u-boot-brain
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bb6b142fc1
We need to ensure that CONFIG_PHYS_64BIT is configured via Kconfig so that it is always available to the build system. Otherwise we can run into cases where we have inconsistent sizes of certain attributes. Ravi Babu reported offset mismatch of struct dwc3 across files since commit95ebc253e6("types.h: move and redefine resource_size_t"). Since the commit, resource_addr_t points to phys_addr_t, whose size is dependent on CONFIG_PHYS_64BIT for ARM architecture. I tried my best to use "select" where possible (for example, ARMv8 architecture) because I think this kind of option is generally user- unconfigurable. However, I see some of PowerPC boards have 36BIT defconfigs as well as 32BIT ones. I moved CONFIG_PHYS_64BIT to the defconfigs for such boards. CONFIG_36BIT is no longer referenced, so all of the defines were removed from CONFIG_SYS_EXTRA_OPTIONS. Fixes:95ebc253e6("types.h: move and redefine resource_size_t") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Ravi Babu <ravibabu@ti.com> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
320 lines
12 KiB
C
320 lines
12 KiB
C
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/************************************************************************
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* katmai.h - configuration for AMCC Katmai (440SPe)
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_KATMAI 1 /* Board is Katmai */
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#define CONFIG_440 1 /* ... PPC440 family */
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#define CONFIG_440SPE 1 /* Specifc SPe support */
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#define CONFIG_440SPE_REVA 1 /* Support old Rev A. */
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
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#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
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#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
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/*
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* Enable this board for more than 2GB of SDRAM
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*/
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#define CONFIG_VERY_BIG_RAM
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/*
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* Include common defines/options for all AMCC eval boards
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*/
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#define CONFIG_HOSTNAME katmai
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#include "amcc-common.h"
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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#undef CONFIG_SHOW_BOOT_PROGRESS
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */
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#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
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#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
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#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
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#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
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#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
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#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
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#define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
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#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
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#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
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#define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000
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#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
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#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
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#define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000
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/* base address of inbound PCIe window */
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#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
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/* System RAM mapped to PCI space */
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#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
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#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
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#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
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#define CONFIG_SYS_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer (placed in internal SRAM)
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_TEMP_STACK_OCM 1
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#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#define CONFIG_CONS_INDEX 1 /* Use UART0 */
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
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#define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/
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#define CONFIG_DDR_ECC 1 /* with ECC support */
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#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* optimal value found by GDA*/
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#undef CONFIG_STRESS
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
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#define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */
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#define IIC0_BOOTPROM_ADDR 0x50
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#define IIC0_ALT_BOOTPROM_ADDR 0x54
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#define CONFIG_SYS_I2C_EEPROM_ADDR (0x50)
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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/* I2C bootstrap EEPROM */
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#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
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#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
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#define CONFIG_4xx_CONFIG_BLOCKSIZE 8
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/* I2C RTC */
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#define CONFIG_RTC_M41T11 1
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#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */
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/* I2C DTT */
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#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
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#define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */
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/*
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* standard dtt sensor configuration - bottom bit will determine local or
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* remote sensor of the ADM1021, the rest determines index into
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* CONFIG_SYS_DTT_ADM1021 array below.
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*/
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#define CONFIG_DTT_SENSORS { 0, 1 }
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/*
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* ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
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* there will be one entry in this array for each two (dummy) sensors in
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* CONFIG_DTT_SENSORS.
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*
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* For Katmai board:
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* - only one ADM1021
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* - i2c addr 0x18
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* - conversion rate 0x02 = 0.25 conversions/second
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* - ALERT ouput disabled
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* - local temp sensor enabled, min set to 0 deg, max set to 85 deg
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* - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
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*/
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#define CONFIG_SYS_DTT_ADM1021 { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
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/*
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* Default environment variables
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_AMCC_DEF_ENV \
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CONFIG_AMCC_DEF_ENV_POWERPC \
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CONFIG_AMCC_DEF_ENV_NOR_UPD \
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"kernel_addr=ff000000\0" \
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"fdt_addr=ff1e0000\0" \
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"ramdisk_addr=ff200000\0" \
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"pciconfighost=1\0" \
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"pcie_mode=RP:RP:RP\0" \
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""
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/*
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* Commands additional to the ones defined in amcc-common.h
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*/
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#define CONFIG_CMD_CHIP_CONFIG
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_ECCTEST
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_SDRAM
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#define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */
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#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
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#define CONFIG_HAS_ETH0
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CONFIG_PHY_RESET_DELAY 1000
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#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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/* General PCI */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
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#define CONFIG_PCI_CONFIG_HOST_BRIDGE
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/* Board-specific PCI */
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#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
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#undef CONFIG_SYS_PCI_MASTER_INIT
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
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/* #define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_DEVICEID */
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/*
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* NETWORK Support (PCI):
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*/
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/* Support for Intel 82557/82559/82559ER chips. */
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#define CONFIG_EEPRO100
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/*-----------------------------------------------------------------------
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* Xilinx System ACE support
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*----------------------------------------------------------------------*/
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#define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */
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#define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */
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#define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE
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#define CONFIG_DOS_PARTITION 1
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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*----------------------------------------------------------------------*/
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/* Memory Bank 0 (Flash) initialization */
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#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
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EBC_BXAP_TWT_ENCODE(7) | \
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EBC_BXAP_BCE_DISABLE | \
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EBC_BXAP_BCT_2TRANS | \
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EBC_BXAP_CSN_ENCODE(0) | \
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EBC_BXAP_OEN_ENCODE(0) | \
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EBC_BXAP_WBN_ENCODE(0) | \
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EBC_BXAP_WBF_ENCODE(0) | \
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EBC_BXAP_TH_ENCODE(0) | \
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EBC_BXAP_RE_DISABLED | \
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EBC_BXAP_SOR_DELAYED | \
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EBC_BXAP_BEM_WRITEONLY | \
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EBC_BXAP_PEN_DISABLED)
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#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
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EBC_BXCR_BS_16MB | \
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EBC_BXCR_BU_RW | \
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EBC_BXCR_BW_16BIT)
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/* Memory Bank 1 (Xilinx System ACE controller) initialization */
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#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
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EBC_BXAP_TWT_ENCODE(4) | \
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EBC_BXAP_BCE_DISABLE | \
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EBC_BXAP_BCT_2TRANS | \
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EBC_BXAP_CSN_ENCODE(0) | \
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EBC_BXAP_OEN_ENCODE(0) | \
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EBC_BXAP_WBN_ENCODE(0) | \
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EBC_BXAP_WBF_ENCODE(0) | \
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EBC_BXAP_TH_ENCODE(0) | \
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EBC_BXAP_RE_DISABLED | \
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EBC_BXAP_SOR_NONDELAYED | \
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EBC_BXAP_BEM_WRITEONLY | \
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EBC_BXAP_PEN_DISABLED)
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#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE) | \
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EBC_BXCR_BS_1MB | \
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EBC_BXCR_BU_RW | \
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EBC_BXCR_BW_16BIT)
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/*-------------------------------------------------------------------------
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* Initialize EBC CONFIG -
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* Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
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* default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
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*-------------------------------------------------------------------------*/
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#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \
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EBC_CFG_PTD_ENABLE | \
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EBC_CFG_RTC_16PERCLK | \
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EBC_CFG_ATC_PREVIOUS | \
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EBC_CFG_DTC_PREVIOUS | \
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EBC_CFG_CTC_PREVIOUS | \
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EBC_CFG_OEO_PREVIOUS | \
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EBC_CFG_EMC_DEFAULT | \
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EBC_CFG_PME_DISABLE | \
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EBC_CFG_PR_16)
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/*-----------------------------------------------------------------------
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* GPIO Setup
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_GPIO_PCIE_PRESENT0 17
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#define CONFIG_SYS_GPIO_PCIE_PRESENT1 21
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#define CONFIG_SYS_GPIO_PCIE_PRESENT2 23
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#define CONFIG_SYS_GPIO_RS232_FORCEOFF 30
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#define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
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GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
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GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
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GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
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#define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
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#define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
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#define CONFIG_SYS_GPIO_ODR 0
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#endif /* __CONFIG_H */
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