mirror of
https://github.com/brain-hackers/u-boot-brain
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7d8e1651da
Some of the setups including cn9130 opens mmio window starting from 0xc0000000, reflect it in the u-boot code. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
115 lines
2.2 KiB
C
115 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <linux/libfdt.h>
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#include <linux/sizes.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/armv8/mmu.h>
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#include <mach/fw_info.h>
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/* Armada 7k/8k */
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#define MVEBU_RFU_BASE (MVEBU_REGISTER(0x6f0000))
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#define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84)
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#define RFU_SW_RESET_OFFSET 0
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#define SAR0_REG (MVEBU_REGISTER(0x2400200))
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#define BOOT_MODE_MASK 0x3f
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#define BOOT_MODE_OFFSET 4
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static struct mm_region mvebu_mem_map[] = {
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/* Armada 80x0 memory regions include the CP1 (slave) units */
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{
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/* RAM 0-64MB */
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.phys = 0x0UL,
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.virt = 0x0UL,
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.size = ATF_REGION_START,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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},
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/* ATF and TEE region 0x4000000-0x5400000 not mapped */
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{
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/* RAM 66MB-2GB */
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.phys = ATF_REGION_END,
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.virt = ATF_REGION_END,
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.size = SZ_2G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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},
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{
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/* MMIO regions */
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.phys = MMIO_REGS_PHY_BASE,
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.virt = MMIO_REGS_PHY_BASE,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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},
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{
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0,
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}
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};
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struct mm_region *mem_map = mvebu_mem_map;
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void enable_caches(void)
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{
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icache_enable();
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dcache_enable();
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}
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void reset_cpu(void)
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{
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u32 reg;
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reg = readl(RFU_GLOBAL_SW_RST);
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reg &= ~(1 << RFU_SW_RESET_OFFSET);
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writel(reg, RFU_GLOBAL_SW_RST);
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}
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/*
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* TODO - implement this functionality using platform
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* clock driver once it gets available
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* Return NAND clock in Hz
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*/
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u32 mvebu_get_nand_clock(void)
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{
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unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL;
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unsigned long NF_CLOCK_SEL_MASK = 0x1;
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u32 reg;
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reg = readl(NAND_FLASH_CLK_CTRL);
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if (reg & NF_CLOCK_SEL_MASK)
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return 400 * 1000000;
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else
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return 250 * 1000000;
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}
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int mmc_get_env_dev(void)
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{
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u32 reg;
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unsigned int boot_mode;
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reg = readl(SAR0_REG);
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boot_mode = (reg >> BOOT_MODE_OFFSET) & BOOT_MODE_MASK;
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switch (boot_mode) {
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case 0x28:
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case 0x2a:
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return 0;
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case 0x29:
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case 0x2b:
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return 1;
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}
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return CONFIG_SYS_MMC_ENV_DEV;
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}
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