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https://github.com/brain-hackers/u-boot-brain
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f51cdaf191
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
64 lines
1.9 KiB
C
64 lines
1.9 KiB
C
/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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void cpu_init_f(void)
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{
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fsl_lbc_t *lbc = LBC_BASE_ADDR;
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/*
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* LCRR - Clock Ratio Register - set up local bus timing
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* when needed
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*/
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out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
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#if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM)
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set_lbc_br(0, CONFIG_NAND_BR_PRELIM);
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set_lbc_or(0, CONFIG_NAND_OR_PRELIM);
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#else
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#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
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#endif
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#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
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ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
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char *l2srbar;
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int i;
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out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
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/* set MBECCDIS=1, SBECCDIS=1 */
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out_be32(&l2cache->l2errdis,
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(MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
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/* set L2E=1 & L2SRAM=001 */
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out_be32(&l2cache->l2ctl,
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(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
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/* Initialize L2 SRAM to zero */
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l2srbar = (char *)CONFIG_SYS_INIT_L2_ADDR;
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for (i = 0; i < CONFIG_SYS_L2_SIZE; i++)
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l2srbar[i] = 0;
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#endif
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}
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