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https://github.com/brain-hackers/u-boot-brain
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![Paul Kocialkowski](/assets/img/avatar_default.png)
Boards using the TWL4030 regulator may not all use the LDOs the same way (e.g. MMC2 power can be controlled by another LDO than VMMC2). This delegates TWL4030 MMC power initializations to board-specific functions, that may still call twl4030_power_mmc_init for the default behavior. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@ti.com> [trini: Fix omap3_evm warning, add twl4030.h] Signed-off-by: Tom Rini <trini@ti.com>
223 lines
4.8 KiB
C
223 lines
4.8 KiB
C
/*
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* Maintainer :
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* Tapani Utriainen <linuxfae@technexion.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <twl4030.h>
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#include <asm/io.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/gpio.h>
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#include <asm/gpio.h>
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#include <asm/mach-types.h>
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#include <usb.h>
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#include <asm/ehci-omap.h>
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#include "tao3530.h"
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DECLARE_GLOBAL_DATA_PTR;
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int tao3530_revision(void)
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{
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int ret = 0;
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/* char *label argument is unused in gpio_request() */
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ret = gpio_request(65, "");
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if (ret) {
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puts("Error: GPIO 65 not available\n");
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goto out;
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}
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MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4));
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ret = gpio_request(1, "");
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if (ret) {
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puts("Error: GPIO 1 not available\n");
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goto out2;
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}
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MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M4));
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ret = gpio_direction_input(65);
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if (ret) {
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puts("Error: GPIO 65 not available for input\n");
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goto out3;
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}
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ret = gpio_direction_input(1);
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if (ret) {
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puts("Error: GPIO 1 not available for input\n");
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goto out3;
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}
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ret = gpio_get_value(65) << 1 | gpio_get_value(1);
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out3:
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MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M0));
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gpio_free(1);
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out2:
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MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0));
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gpio_free(65);
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out:
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return ret;
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}
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#ifdef CONFIG_SPL_BUILD
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/*
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* Routine: get_board_mem_timings
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* Description: If we use SPL then there is no x-loader nor config header
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* so we have to setup the DDR timings ourself on both banks.
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*/
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void get_board_mem_timings(struct board_sdrc_timings *timings)
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{
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#if defined(CONFIG_SYS_BOARD_OMAP3_HA)
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/*
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* Switch baseboard LED to red upon power-on
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*/
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MUX_OMAP3_HA();
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/* Request a gpio before using it */
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gpio_request(111, "");
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/* Sets the gpio as output and its value to 1, switch LED to red */
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gpio_direction_output(111, 1);
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#endif
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if (tao3530_revision() < 3) {
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/* 256MB / Bank */
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timings->mcfg = MCFG(256 << 20, 14); /* RAS-width 14 */
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timings->ctrla = HYNIX_V_ACTIMA_165;
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timings->ctrlb = HYNIX_V_ACTIMB_165;
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} else {
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/* 128MB / Bank */
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timings->mcfg = MCFG(128 << 20, 13); /* RAS-width 13 */
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timings->ctrla = MICRON_V_ACTIMA_165;
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timings->ctrlb = MICRON_V_ACTIMB_165;
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}
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timings->mr = MICRON_V_MR_165;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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}
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#endif
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* board id for Linux */
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gd->bd->bi_arch_number = MACH_TYPE_OMAP3_TAO3530;
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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return 0;
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}
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/*
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* Routine: misc_init_r
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* Description: Configure board specific parts
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*/
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int misc_init_r(void)
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{
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struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
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struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
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twl4030_power_init();
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twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
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/* Configure GPIOs to output */
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/* GPIO23 */
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writel(~(GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
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writel(~(GPIO31 | GPIO30 | GPIO22 | GPIO21 |
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GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
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/* Set GPIOs */
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writel(GPIO10 | GPIO8 | GPIO2 | GPIO1,
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&gpio6_base->setdataout);
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writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
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GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
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switch (tao3530_revision()) {
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case 0:
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puts("TAO-3530 REV Reserve 1\n");
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break;
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case 1:
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puts("TAO-3530 REV Reserve 2\n");
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break;
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case 2:
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puts("TAO-3530 REV Cx\n");
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break;
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case 3:
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puts("TAO-3530 REV Ax/Bx\n");
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break;
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default:
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puts("Unknown board revision\n");
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}
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dieid_num_r();
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return 0;
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}
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_TAO3530();
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#if defined(CONFIG_SYS_BOARD_OMAP3_HA)
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MUX_OMAP3_HA();
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#endif
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}
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#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
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int board_mmc_init(bd_t *bis)
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{
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omap_mmc_init(0, 0, 0, -1, -1);
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return 0;
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}
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#endif
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#if defined(CONFIG_GENERIC_MMC)
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void board_mmc_power_init(void)
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{
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twl4030_power_mmc_init(0);
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}
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#endif
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#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
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/* Call usb_stop() before starting the kernel */
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void show_boot_progress(int val)
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{
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if (val == BOOTSTAGE_ID_RUN_OS)
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usb_stop();
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}
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static struct omap_usbhs_board_data usbhs_bdata = {
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.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
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.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
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.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
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};
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
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}
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int ehci_hcd_stop(int index)
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{
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return omap_ehci_hcd_stop();
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}
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#endif /* CONFIG_USB_EHCI */
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