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https://github.com/brain-hackers/u-boot-brain
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f8d25d7466
This patch adds the DDR3 setup and training code taken from the Marvell U-Boot repository. This code used to be included as a binary (bin_hdr) into the AXP boot image. Not linked with the main U-Boot. With this code addition and the following serdes/PHY setup code, the Armada-XP support in mainline U-Boot is finally self-contained. So the complete image for booting can be built from mainline U-Boot. Without any additional external inclusion. Hopefully other MVEBU SoC's will follow here. Support for some SoC's has been removed in this version. This is: MV_MSYS: The code referred to by the MV_MSYS define is currently unused. And its not really planned to support this in mainline. So lets remove it to make the code clearer and increase the readability. MV88F68XX (A38x): The code referred to by the MV88F68XX define (A38x) is currently unused. And its partial and not sufficient for this device in this stage. So lets remove it to make the code clearer and increase the readability. MV88F66XX (ALP): The code referred to by the MV88F66XX define is currently unused. And its not really planned to support this in mainline. So lets remove it to make the code clearer and increase the readability. MV88F78X60_Z1: The code referred to by the MV88F78X60_Z1 define is currently unused. As the Z1 revision of the AXP is not supported in mainline anymore. So lets remove it to make the code clearer and increase the readability. Remove support for Z1 & A0 AXP revisions (steppings). The current stepping is B0 and this is the only one that is actively supported in this code version. Tested on AXP using a SPD DIMM setup on the Marvell DB-MV784MP-GP board and on a custom fixed DDR configuration board (maxbcm). Note: This code has undergone many hours of coding-style cleanup and refactoring. It still is not checkpatch clean though, I'm afraid. As the factoring of the code has so many levels of indentation that many lines are longer than 80 chars. This might be some task to tackly later on. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
71 lines
2.2 KiB
C
71 lines
2.2 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __XOR_H
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#define __XOR_H
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#include "ddr3_hw_training.h"
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#define MV_XOR_MAX_CHAN 4 /* total channels for all units together */
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/*
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* This enumerator describes the type of functionality the XOR channel
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* can have while using the same data structures.
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*/
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enum xor_type {
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MV_XOR, /* XOR channel functions as XOR accelerator */
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MV_DMA, /* XOR channel functions as IDMA channel */
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MV_CRC32 /* XOR channel functions as CRC 32 calculator */
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};
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/*
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* This enumerator describes the set of commands that can be applied on
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* an engine (e.g. IDMA, XOR). Appling a comman depends on the current
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* status (see MV_STATE enumerator)
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* Start can be applied only when status is IDLE
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* Stop can be applied only when status is IDLE, ACTIVE or PAUSED
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* Pause can be applied only when status is ACTIVE
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* Restart can be applied only when status is PAUSED
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*/
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enum mv_command {
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MV_START, /* Start */
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MV_STOP, /* Stop */
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MV_PAUSE, /* Pause */
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MV_RESTART /* Restart */
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};
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/*
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* This enumerator describes the set of state conditions.
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* Moving from one state to other is stricted.
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*/
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enum mv_state {
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MV_IDLE,
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MV_ACTIVE,
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MV_PAUSED,
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MV_UNDEFINED_STATE
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};
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/* XOR descriptor structure for CRC and DMA descriptor */
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struct crc_dma_desc {
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u32 status; /* Successful descriptor execution indication */
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u32 crc32_result; /* Result of CRC-32 calculation */
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u32 desc_cmd; /* type of operation to be carried out on the data */
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u32 next_desc_ptr; /* Next descriptor address pointer */
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u32 byte_cnt; /* Size of source block part represented by the descriptor */
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u32 dst_addr; /* Destination Block address pointer (not used in CRC32 */
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u32 src_addr0; /* Mode: Source Block address pointer */
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u32 src_addr1; /* Mode: Source Block address pointer */
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} __packed;
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int mv_xor_state_get(u32 chan);
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void mv_sys_xor_init(MV_DRAM_INFO *dram_info);
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void mv_sys_xor_finish(void);
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int mv_xor_transfer(u32 chan, int xor_type, u32 xor_chain_ptr);
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int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, u32 init_val_high,
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u32 init_val_low);
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#endif /* __XOR_H */
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