mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 19:26:16 +09:00
![]() Set TXFIFOTHRESH to adjust ddr pipeline delay for successful large usb writes Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
||
---|---|---|
.. | ||
cpu | ||
include/asm | ||
lib | ||
config.mk | ||
Kconfig |