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![Tom Rix](/assets/img/avatar_default.png)
The twl4030 provides a PHY device for connecting a link device, like musb, to physical connection. This change adds the twl4030 usb registers and functions for initializing the PHY as required by omap3. Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
190 lines
5.7 KiB
C
190 lines
5.7 KiB
C
/*
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* Copyright (c) 2009 Wind River Systems, Inc.
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* Tom Rix <Tom.Rix@windriver.com>
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*
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* This is file is based on
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* repository git.gitorious.org/u-boot-omap3/mainline.git,
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* branch omap3-dev-usb, file drivers/usb/gadget/twl4030_usb.c
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*
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* This is the unique part of its copyright :
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*
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* ------------------------------------------------------------------------
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*
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* * (C) Copyright 2009 Atin Malaviya (atin.malaviya@gmail.com)
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*
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* Based on: twl4030_usb.c in linux 2.6 (drivers/i2c/chips/twl4030_usb.c)
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* Copyright (C) 2004-2007 Texas Instruments
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* Copyright (C) 2008 Nokia Corporation
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* Contact: Felipe Balbi <felipe.balbi@nokia.com>
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*
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* Author: Atin Malaviya (atin.malaviya@gmail.com)
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*
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* ------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <twl4030.h>
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/* Defines for bits in registers */
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#define OPMODE_MASK (3 << 3)
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#define XCVRSELECT_MASK (3 << 0)
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#define CARKITMODE (1 << 2)
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#define OTG_ENAB (1 << 5)
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#define PHYPWD (1 << 0)
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#define CLOCKGATING_EN (1 << 2)
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#define CLK32K_EN (1 << 1)
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#define REQ_PHY_DPLL_CLK (1 << 0)
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#define PHY_DPLL_CLK (1 << 0)
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static int twl4030_usb_write(u8 address, u8 data)
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{
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int ret;
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ret = twl4030_i2c_write_u8(TWL4030_CHIP_USB, data, address);
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if (ret != 0)
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printf("TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
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return ret;
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}
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static int twl4030_usb_read(u8 address)
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{
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u8 data;
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int ret;
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ret = twl4030_i2c_read_u8(TWL4030_CHIP_USB, &data, address);
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if (ret == 0)
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ret = data;
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else
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printf("TWL4030:USB:Read[0x%x] Error %d\n", address, ret);
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return ret;
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}
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static void twl4030_usb_ldo_init(void)
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{
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/* Enable writing to power configuration registers */
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twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0xC0,
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TWL4030_PM_MASTER_PROTECT_KEY);
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twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x0C,
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TWL4030_PM_MASTER_PROTECT_KEY);
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/* put VUSB3V1 LDO in active state */
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twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00,
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TWL4030_PM_RECEIVER_VUSB_DEDICATED2);
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/* input to VUSB3V1 LDO is from VBAT, not VBUS */
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twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x14,
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TWL4030_PM_RECEIVER_VUSB_DEDICATED1);
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/* turn on 3.1V regulator */
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twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20,
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TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP);
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twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00,
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TWL4030_PM_RECEIVER_VUSB3V1_TYPE);
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/* turn on 1.5V regulator */
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twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20,
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TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP);
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twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00,
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TWL4030_PM_RECEIVER_VUSB1V5_TYPE);
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/* turn on 1.8V regulator */
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twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20,
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TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP);
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twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00,
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TWL4030_PM_RECEIVER_VUSB1V8_TYPE);
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/* disable access to power configuration registers */
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twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x00,
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TWL4030_PM_MASTER_PROTECT_KEY);
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}
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static void twl4030_phy_power(void)
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{
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u8 pwr, clk;
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/* Power the PHY */
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pwr = twl4030_usb_read(TWL4030_USB_PHY_PWR_CTRL);
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pwr &= ~PHYPWD;
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twl4030_usb_write(TWL4030_USB_PHY_PWR_CTRL, pwr);
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/* Enable clocks */
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clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL);
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clk |= CLOCKGATING_EN | CLK32K_EN;
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twl4030_usb_write(TWL4030_USB_PHY_CLK_CTRL, clk);
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}
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/*
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* Initiaze the ULPI interface
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* ULPI : Universal Transceiver Macrocell Low Pin Interface
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* An interface between the USB link controller like musb and the
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* the PHY or transceiver that drives the actual bus.
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*/
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int twl4030_usb_ulpi_init(void)
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{
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long timeout = 1000 * 1000; /* 1 sec */;
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u8 clk, sts, pwr;
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/* twl4030 ldo init */
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twl4030_usb_ldo_init();
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/* Enable the twl4030 phy */
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twl4030_phy_power();
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/* Enable DPLL to access PHY registers over I2C */
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clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL);
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clk |= REQ_PHY_DPLL_CLK;
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twl4030_usb_write(TWL4030_USB_PHY_CLK_CTRL, clk);
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/* Check if the PHY DPLL is locked */
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sts = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL_STS);
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while (!(sts & PHY_DPLL_CLK) && 0 < timeout) {
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udelay(10);
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sts = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL_STS);
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timeout -= 10;
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}
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/* Final check */
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sts = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL_STS);
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if (!(sts & PHY_DPLL_CLK)) {
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printf("Error:TWL4030:USB Timeout setting PHY DPLL clock\n");
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return -1;
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}
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/*
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* There are two circuit blocks attached to the PHY,
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* Carkit and USB OTG. Disable Carkit and enable USB OTG
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*/
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twl4030_usb_write(TWL4030_USB_IFC_CTRL_CLR, CARKITMODE);
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pwr = twl4030_usb_read(TWL4030_USB_POWER_CTRL);
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pwr |= OTG_ENAB;
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twl4030_usb_write(TWL4030_USB_POWER_CTRL_SET, pwr);
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/* Clear the opmode bits to ensure normal encode */
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twl4030_usb_write(TWL4030_USB_FUNC_CTRL_CLR, OPMODE_MASK);
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/* Clear the xcvrselect bits to enable the high speed transeiver */
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twl4030_usb_write(TWL4030_USB_FUNC_CTRL_CLR, XCVRSELECT_MASK);
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/* Let ULPI control the DPLL clock */
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clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL);
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clk &= ~REQ_PHY_DPLL_CLK;
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twl4030_usb_write(TWL4030_USB_PHY_CLK_CTRL, clk);
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return 0;
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}
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