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https://github.com/brain-hackers/u-boot-brain
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![Srikanth Thokala](/assets/img/avatar_default.png)
Added d-cache support for zynq_gem.c, Observed a difference of +0.8 MiB/s when downloading a file of size of 3007944Bytes. With d-cache OFF: ---------------- Filename 'uImage'. Load address: 0x800 Loading: ################################################################# ################################################################# ################################################################# ########## 1.3 MiB/s done Bytes transferred = 3007944 (2de5c8 hex) With d-cache ON: --------------- Filename 'uImage'. Load address: 0x800 Loading: ################################################################# ################################################################# ################################################################# ########## 2.1 MiB/s done Bytes transferred = 3007944 (2de5c8 hex) Changes on zynq_gem for d-cache support: - Tx and Rx buffers are cache-aligned - Updated logic for invalidating Rx buffers and flushing Tx buffers. - Tx and Rx BD's are allocated from non-cacheable region. (When BDs are cached, we don't see a consistent link) - Use TX BD status intead of txsr status checks. Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
530 lines
14 KiB
C
530 lines
14 KiB
C
/*
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* (C) Copyright 2011 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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* Based on Xilinx gmac driver:
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* (C) Copyright 2011 Xilinx
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <net.h>
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#include <config.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <phy.h>
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#include <miiphy.h>
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#include <watchdog.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#if !defined(CONFIG_PHYLIB)
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# error XILINX_GEM_ETHERNET requires PHYLIB
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#endif
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/* Bit/mask specification */
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#define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
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#define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
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#define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
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#define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
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#define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
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#define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
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#define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
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#define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
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#define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
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#define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
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#define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
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/* Wrap bit, last descriptor */
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#define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
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#define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
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#define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
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#define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
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#define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
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#define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
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#define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */
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#define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
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#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
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#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
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#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
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#define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */
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#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_FDEN | \
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ZYNQ_GEM_NWCFG_FSREM | \
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ZYNQ_GEM_NWCFG_MDCCLKDIV)
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#define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
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#define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
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/* Use full configured addressable space (8 Kb) */
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#define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
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/* Use full configured addressable space (4 Kb) */
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#define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
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/* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
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#define ZYNQ_GEM_DMACR_RXBUF 0x00180000
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#define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
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ZYNQ_GEM_DMACR_RXSIZE | \
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ZYNQ_GEM_DMACR_TXSIZE | \
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ZYNQ_GEM_DMACR_RXBUF)
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/* Use MII register 1 (MII status register) to detect PHY */
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#define PHY_DETECT_REG 1
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/* Mask used to verify certain PHY features (or register contents)
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* in the register above:
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* 0x1000: 10Mbps full duplex support
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* 0x0800: 10Mbps half duplex support
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* 0x0008: Auto-negotiation support
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*/
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#define PHY_DETECT_MASK 0x1808
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/* TX BD status masks */
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#define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
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#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
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#define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
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/* Device registers */
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struct zynq_gem_regs {
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u32 nwctrl; /* Network Control reg */
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u32 nwcfg; /* Network Config reg */
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u32 nwsr; /* Network Status reg */
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u32 reserved1;
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u32 dmacr; /* DMA Control reg */
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u32 txsr; /* TX Status reg */
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u32 rxqbase; /* RX Q Base address reg */
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u32 txqbase; /* TX Q Base address reg */
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u32 rxsr; /* RX Status reg */
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u32 reserved2[2];
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u32 idr; /* Interrupt Disable reg */
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u32 reserved3;
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u32 phymntnc; /* Phy Maintaince reg */
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u32 reserved4[18];
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u32 hashl; /* Hash Low address reg */
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u32 hashh; /* Hash High address reg */
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#define LADDR_LOW 0
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#define LADDR_HIGH 1
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u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */
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u32 match[4]; /* Type ID1 Match reg */
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u32 reserved6[18];
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u32 stat[44]; /* Octects transmitted Low reg - stat start */
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};
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/* BD descriptors */
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struct emac_bd {
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u32 addr; /* Next descriptor pointer */
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u32 status;
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};
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#define RX_BUF 3
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/* Page table entries are set to 1MB, or multiples of 1MB
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* (not < 1MB). driver uses less bd's so use 1MB bdspace.
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*/
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#define BD_SPACE 0x100000
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/* BD separation space */
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#define BD_SEPRN_SPACE 64
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/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
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struct zynq_gem_priv {
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struct emac_bd *tx_bd;
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struct emac_bd *rx_bd;
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char *rxbuffers;
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u32 rxbd_current;
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u32 rx_first_buf;
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int phyaddr;
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u32 emio;
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int init;
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struct phy_device *phydev;
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struct mii_dev *bus;
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};
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static inline int mdio_wait(struct eth_device *dev)
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{
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struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
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u32 timeout = 200;
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/* Wait till MDIO interface is ready to accept a new transaction. */
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while (--timeout) {
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if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
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break;
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WATCHDOG_RESET();
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}
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if (!timeout) {
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printf("%s: Timeout\n", __func__);
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return 1;
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}
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return 0;
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}
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static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
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u32 op, u16 *data)
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{
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u32 mgtcr;
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struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
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if (mdio_wait(dev))
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return 1;
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/* Construct mgtcr mask for the operation */
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mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
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(phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
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(regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
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/* Write mgtcr and wait for completion */
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writel(mgtcr, ®s->phymntnc);
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if (mdio_wait(dev))
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return 1;
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if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
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*data = readl(®s->phymntnc);
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return 0;
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}
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static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
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{
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return phy_setup_op(dev, phy_addr, regnum,
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ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
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}
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static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
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{
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return phy_setup_op(dev, phy_addr, regnum,
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ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
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}
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static void phy_detection(struct eth_device *dev)
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{
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int i;
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u16 phyreg;
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struct zynq_gem_priv *priv = dev->priv;
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if (priv->phyaddr != -1) {
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phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);
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if ((phyreg != 0xFFFF) &&
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((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
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/* Found a valid PHY address */
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debug("Default phy address %d is valid\n",
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priv->phyaddr);
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return;
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} else {
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debug("PHY address is not setup correctly %d\n",
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priv->phyaddr);
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priv->phyaddr = -1;
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}
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}
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debug("detecting phy address\n");
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if (priv->phyaddr == -1) {
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/* detect the PHY address */
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for (i = 31; i >= 0; i--) {
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phyread(dev, i, PHY_DETECT_REG, &phyreg);
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if ((phyreg != 0xFFFF) &&
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((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
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/* Found a valid PHY address */
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priv->phyaddr = i;
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debug("Found valid phy address, %d\n", i);
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return;
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}
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}
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}
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printf("PHY is not detected\n");
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}
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static int zynq_gem_setup_mac(struct eth_device *dev)
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{
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u32 i, macaddrlow, macaddrhigh;
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struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
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/* Set the MAC bits [31:0] in BOT */
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macaddrlow = dev->enetaddr[0];
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macaddrlow |= dev->enetaddr[1] << 8;
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macaddrlow |= dev->enetaddr[2] << 16;
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macaddrlow |= dev->enetaddr[3] << 24;
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/* Set MAC bits [47:32] in TOP */
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macaddrhigh = dev->enetaddr[4];
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macaddrhigh |= dev->enetaddr[5] << 8;
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for (i = 0; i < 4; i++) {
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writel(0, ®s->laddr[i][LADDR_LOW]);
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writel(0, ®s->laddr[i][LADDR_HIGH]);
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/* Do not use MATCHx register */
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writel(0, ®s->match[i]);
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}
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writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
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writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
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return 0;
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}
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static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
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{
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u32 i, rclk, clk = 0;
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struct phy_device *phydev;
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const u32 stat_size = (sizeof(struct zynq_gem_regs) -
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offsetof(struct zynq_gem_regs, stat)) / 4;
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struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
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struct zynq_gem_priv *priv = dev->priv;
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const u32 supported = SUPPORTED_10baseT_Half |
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SUPPORTED_10baseT_Full |
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SUPPORTED_100baseT_Half |
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SUPPORTED_100baseT_Full |
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SUPPORTED_1000baseT_Half |
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SUPPORTED_1000baseT_Full;
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if (!priv->init) {
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/* Disable all interrupts */
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writel(0xFFFFFFFF, ®s->idr);
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/* Disable the receiver & transmitter */
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writel(0, ®s->nwctrl);
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writel(0, ®s->txsr);
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writel(0, ®s->rxsr);
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writel(0, ®s->phymntnc);
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/* Clear the Hash registers for the mac address
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* pointed by AddressPtr
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*/
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writel(0x0, ®s->hashl);
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/* Write bits [63:32] in TOP */
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writel(0x0, ®s->hashh);
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/* Clear all counters */
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for (i = 0; i <= stat_size; i++)
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readl(®s->stat[i]);
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/* Setup RxBD space */
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memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
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for (i = 0; i < RX_BUF; i++) {
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priv->rx_bd[i].status = 0xF0000000;
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priv->rx_bd[i].addr =
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((u32)(priv->rxbuffers) +
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(i * PKTSIZE_ALIGN));
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}
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/* WRAP bit to last BD */
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priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
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/* Write RxBDs to IP */
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writel((u32)priv->rx_bd, ®s->rxqbase);
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/* Setup for DMA Configuration register */
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writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
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/* Setup for Network Control register, MDIO, Rx and Tx enable */
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setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
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priv->init++;
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}
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phy_detection(dev);
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/* interface - look at tsec */
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phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
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phydev->supported = supported | ADVERTISED_Pause |
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ADVERTISED_Asym_Pause;
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phydev->advertising = phydev->supported;
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priv->phydev = phydev;
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phy_config(phydev);
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phy_startup(phydev);
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switch (phydev->speed) {
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case SPEED_1000:
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writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
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®s->nwcfg);
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rclk = (0 << 4) | (1 << 0);
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clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
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break;
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case SPEED_100:
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clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
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ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
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rclk = 1 << 0;
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clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
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break;
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case SPEED_10:
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rclk = 1 << 0;
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/* FIXME untested */
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clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
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break;
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}
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/* Change the rclk and clk only not using EMIO interface */
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if (!priv->emio)
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zynq_slcr_gem_clk_setup(dev->iobase !=
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ZYNQ_GEM_BASEADDR0, rclk, clk);
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setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
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ZYNQ_GEM_NWCTRL_TXEN_MASK);
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return 0;
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}
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static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
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{
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u32 addr, size;
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struct zynq_gem_priv *priv = dev->priv;
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struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
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/* setup BD */
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writel((u32)priv->tx_bd, ®s->txqbase);
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/* Setup Tx BD */
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memset(priv->tx_bd, 0, sizeof(struct emac_bd));
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priv->tx_bd->addr = (u32)ptr;
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priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
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ZYNQ_GEM_TXBUF_LAST_MASK;
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addr = (u32) ptr;
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addr &= ~(ARCH_DMA_MINALIGN - 1);
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size = roundup(len, ARCH_DMA_MINALIGN);
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flush_dcache_range(addr, addr + size);
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barrier();
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/* Start transmit */
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setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
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/* Read TX BD status */
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if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN)
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printf("TX underrun\n");
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if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
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printf("TX buffers exhausted in mid frame\n");
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return 0;
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}
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/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
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static int zynq_gem_recv(struct eth_device *dev)
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{
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int frame_len;
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struct zynq_gem_priv *priv = dev->priv;
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struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
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struct emac_bd *first_bd;
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if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
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return 0;
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if (!(current_bd->status &
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(ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
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printf("GEM: SOF or EOF not set for last buffer received!\n");
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return 0;
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}
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frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
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if (frame_len) {
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u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
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addr &= ~(ARCH_DMA_MINALIGN - 1);
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u32 size = roundup(frame_len, ARCH_DMA_MINALIGN);
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invalidate_dcache_range(addr, addr + size);
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NetReceive((u8 *)addr, frame_len);
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if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
|
|
priv->rx_first_buf = priv->rxbd_current;
|
|
else {
|
|
current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
|
|
current_bd->status = 0xF0000000; /* FIXME */
|
|
}
|
|
|
|
if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
|
|
first_bd = &priv->rx_bd[priv->rx_first_buf];
|
|
first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
|
|
first_bd->status = 0xF0000000;
|
|
}
|
|
|
|
if ((++priv->rxbd_current) >= RX_BUF)
|
|
priv->rxbd_current = 0;
|
|
}
|
|
|
|
return frame_len;
|
|
}
|
|
|
|
static void zynq_gem_halt(struct eth_device *dev)
|
|
{
|
|
struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
|
|
|
|
clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
|
|
ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
|
|
}
|
|
|
|
static int zynq_gem_miiphyread(const char *devname, uchar addr,
|
|
uchar reg, ushort *val)
|
|
{
|
|
struct eth_device *dev = eth_get_dev();
|
|
int ret;
|
|
|
|
ret = phyread(dev, addr, reg, val);
|
|
debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
|
|
return ret;
|
|
}
|
|
|
|
static int zynq_gem_miiphy_write(const char *devname, uchar addr,
|
|
uchar reg, ushort val)
|
|
{
|
|
struct eth_device *dev = eth_get_dev();
|
|
|
|
debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
|
|
return phywrite(dev, addr, reg, val);
|
|
}
|
|
|
|
int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio)
|
|
{
|
|
struct eth_device *dev;
|
|
struct zynq_gem_priv *priv;
|
|
void *bd_space;
|
|
|
|
dev = calloc(1, sizeof(*dev));
|
|
if (dev == NULL)
|
|
return -1;
|
|
|
|
dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
|
|
if (dev->priv == NULL) {
|
|
free(dev);
|
|
return -1;
|
|
}
|
|
priv = dev->priv;
|
|
|
|
/* Align rxbuffers to ARCH_DMA_MINALIGN */
|
|
priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
|
|
memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
|
|
|
|
/* Align bd_space to 1MB */
|
|
bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
|
|
mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF);
|
|
|
|
/* Initialize the bd spaces for tx and rx bd's */
|
|
priv->tx_bd = (struct emac_bd *)bd_space;
|
|
priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE);
|
|
|
|
priv->phyaddr = phy_addr;
|
|
priv->emio = emio;
|
|
|
|
sprintf(dev->name, "Gem.%x", base_addr);
|
|
|
|
dev->iobase = base_addr;
|
|
|
|
dev->init = zynq_gem_init;
|
|
dev->halt = zynq_gem_halt;
|
|
dev->send = zynq_gem_send;
|
|
dev->recv = zynq_gem_recv;
|
|
dev->write_hwaddr = zynq_gem_setup_mac;
|
|
|
|
eth_register(dev);
|
|
|
|
miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
|
|
priv->bus = miiphy_get_dev_by_name(dev->name);
|
|
|
|
return 1;
|
|
}
|