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f3b84a3032
Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself. Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used. Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Removed fsp,mrc-debug-msg and fsp,enable-xhci for minnowmax, bayleybay Fixed lines >80col Signed-off-by: Simon Glass <sjg@chromium.org>
159 lines
3.5 KiB
Plaintext
159 lines
3.5 KiB
Plaintext
Intel Bay Trail FSP UPD Binding
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===============================
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The device tree node which describes the overriding of the Intel Bay Trail FSP
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UPD data for configuring the SoC.
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All properties can be found within the `upd-region` struct in
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arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h, under the same names, and in
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Intel's FSP Binary Configuration Tool for Bay Trail. This list of properties is
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matched up to Intel's E3800 FSPv4 release.
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# Boolean properties:
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- fsp,enable-sdio
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- fsp,enable-sdcard
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- fsp,enable-hsuart0
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- fsp,enable-hsuart1
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- fsp,enable-spi
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- fsp,enable-sata
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- fsp,enable-azalia
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- fsp,enable-xhci
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- fsp,enable-lpe
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- fsp,lpss-sio-enable-pci-mode
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- fsp,enable-dma0
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- fsp,enable-dma1
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- fsp,enable-i2-c0
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- fsp,enable-i2-c1
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- fsp,enable-i2-c2
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- fsp,enable-i2-c3
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- fsp,enable-i2-c4
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- fsp,enable-i2-c5
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- fsp,enable-i2-c6
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- fsp,enable-pwm0
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- fsp,enable-pwm1
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- fsp,enable-hsi
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- fsp,mrc-debug-msg
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- fsp,isp-enable
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- fsp,scc-enable-pci-mode
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- fsp,igd-render-standby
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- fsp,txe-uma-enable
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- fsp,emmc45-ddr50-enabled
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- fsp,emmc45-hs200-enabled
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- fsp,enable-igd
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- fsp,enable-memory-down
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If you set "fsp,enable-memory-down" you are strongly encouraged to provide an
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"fsp,memory-down-params{};" to specify how your memory is configured. If you do
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not set "fsp,enable-memory-down", then the DIMM SPD information will be
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discovered by the FSP and used to setup main memory.
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# Integer properties:
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- fsp,mrc-init-tseg-size
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- fsp,mrc-init-mmio-size
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- fsp,mrc-init-spd-addr1
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- fsp,mrc-init-spd-addr2
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- fsp,emmc-boot-mode
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- fsp,sata-mode
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- fsp,igd-dvmt50-pre-alloc
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- fsp,aperture-size
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- fsp,gtt-size
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- fsp,serial-debug-port-address
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- fsp,serial-debug-port-type
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- fsp,os-selection
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- fsp,emmc45-retune-timer-value
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- fsp,memory-down-params {
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# Boolean properties:
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- fsp,dimm-0-enable
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- fsp,dimm-1-enable
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# Integer properties:
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- fsp,dram-speed
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- fsp,dram-type
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- fsp,dimm-width
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- fsp,dimm-density
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- fsp,dimm-bus-width
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- fsp,dimm-sides
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- fsp,dimm-tcl
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- fsp,dimm-trpt-rcd
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- fsp,dimm-twr
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- fsp,dimm-twtr
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- fsp,dimm-trrd
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- fsp,dimm-trtp
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- fsp,dimm-tfaw
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};
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Example (from MinnowMax Dual Core):
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-----------------------------------
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/ {
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...
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fsp {
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compatible = "intel,baytrail-fsp";
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fsp,mrc-init-tseg-size = <0>;
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fsp,mrc-init-mmio-size = <0x800>;
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fsp,mrc-init-spd-addr1 = <0xa0>;
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fsp,mrc-init-spd-addr2 = <0xa2>;
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fsp,emmc-boot-mode = <2>;
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fsp,enable-sdio;
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fsp,enable-sdcard;
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fsp,enable-hsuart1;
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fsp,enable-spi;
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fsp,enable-sata;
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fsp,sata-mode = <1>;
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fsp,enable-xhci;
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fsp,enable-lpe;
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fsp,lpss-sio-enable-pci-mode;
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fsp,enable-dma0;
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fsp,enable-dma1;
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fsp,enable-i2c0;
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fsp,enable-i2c1;
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fsp,enable-i2c2;
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fsp,enable-i2c3;
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fsp,enable-i2c4;
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fsp,enable-i2c5;
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fsp,enable-i2c6;
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fsp,enable-pwm0;
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fsp,enable-pwm1;
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fsp,igd-dvmt50-pre-alloc = <2>;
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fsp,aperture-size = <2>;
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fsp,gtt-size = <2>;
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fsp,serial-debug-port-address = <0x3f8>;
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fsp,serial-debug-port-type = <1>;
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fsp,mrc-debug-msg;
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fsp,scc-enable-pci-mode;
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fsp,os-selection = <4>;
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fsp,emmc45-ddr50-enabled;
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fsp,emmc45-retune-timer-value = <8>;
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fsp,enable-igd;
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fsp,enable-memory-down;
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fsp,memory-down-params {
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compatible = "intel,baytrail-fsp-mdp";
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fsp,dram-speed = <1>;
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fsp,dram-type = <1>;
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fsp,dimm-0-enable;
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fsp,dimm-width = <1>;
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fsp,dimm-density = <2>;
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fsp,dimm-bus-width = <3>;
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fsp,dimm-sides = <0>;
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fsp,dimm-tcl = <0xb>;
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fsp,dimm-trpt-rcd = <0xb>;
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fsp,dimm-twr = <0xc>;
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fsp,dimm-twtr = <6>;
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fsp,dimm-trrd = <6>;
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fsp,dimm-trtp = <6>;
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fsp,dimm-tfaw = <0x14>;
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};
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};
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...
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};
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