mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
e895a4b06f
This function can fail if the device tree runs out of space. Rather than silently booting with an incomplete device tree, allow the failure to be detected. Unfortunately this involves changing a lot of places in the code. I have not changed behvaiour to return an error where one is not currently returned, to avoid unexpected breakage. Eventually it would be nice to allow boards to register functions to be called to update the device tree. This would avoid all the many functions to do this. However it's not clear yet if this should be done using driver model or with a linker list. This work is left for later. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
269 lines
6.4 KiB
C
269 lines
6.4 KiB
C
/*
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* (C) Copyright 2003-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* (C) Copyright 2006
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* MicroSys GmbH
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*
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* (C) Copyright 2009
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* Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <pci.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <mb862xx.h>
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#include <video_fb.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#ifdef CONFIG_OF_LIBFDT
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#include <fdt_support.h>
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#endif /* CONFIG_OF_LIBFDT */
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/* mt46v16m16-75 */
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#ifdef CONFIG_MPC5200_DDR
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/* Settings for XLB = 132 MHz */
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#define SDRAM_MODE 0x018D0000
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#define SDRAM_EMODE 0x40090000
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#define SDRAM_CONTROL 0x714f0f00
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#define SDRAM_CONFIG1 0x73722930
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#define SDRAM_CONFIG2 0x47770000
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#define SDRAM_TAPDELAY 0x10000000
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#else
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#error SDRAM is not supported on this board
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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static void sdram_start (int hi_addr)
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{
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struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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/* unlock mode register */
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out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
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/* precharge all banks */
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out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
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/* set mode register: extended mode */
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out_be32 (&sdram->mode, SDRAM_EMODE);
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/* set mode register: reset DLL */
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out_be32 (&sdram->mode, SDRAM_MODE | 0x04000000);
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/* precharge all banks */
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out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
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/* auto refresh */
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out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
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/* set mode register */
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out_be32 (&sdram->mode, SDRAM_MODE);
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/* normal operation */
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out_be32 (&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
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}
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/*
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* ATTENTION: Although partially referenced initdram does NOT make real
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* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
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* CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
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*/
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phys_size_t initdram (int board_type)
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{
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struct mpc5xxx_mmap_ctl *mmap_ctl =
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(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
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struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
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struct mpc5xxx_cdm *cdm = (struct mpc5xxx_cdm *)MPC5XXX_CDM;
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ulong dramsize = 0;
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ulong dramsize2 = 0;
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ulong test1, test2;
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/* setup SDRAM chip selects */
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out_be32 (&mmap_ctl->sdram0, 0x0000001e); /* 2G at 0x0 */
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out_be32 (&mmap_ctl->sdram1, 0x00000000); /* disabled */
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/* setup config registers */
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out_be32 (&sdram->config1, SDRAM_CONFIG1);
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out_be32 (&sdram->config2, SDRAM_CONFIG2);
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/* set tap delay */
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out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
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/* find RAM size using SDRAM CS0 only */
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sdram_start (0);
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test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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sdram_start (1);
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test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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if (test1 > test2) {
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sdram_start (0);
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dramsize = test1;
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} else {
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dramsize = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize < (1 << 20))
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dramsize = 0;
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/* set SDRAM CS0 size according to the amount of RAM found */
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if (dramsize > 0)
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out_be32 (&mmap_ctl->sdram0,
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0x13 + __builtin_ffs (dramsize >> 20) - 1);
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else
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out_be32 (&mmap_ctl->sdram1, 0); /* disabled */
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/*
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* On MPC5200B we need to set the special configuration delay in the
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* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
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* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
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*
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* "The SDelay should be written to a value of 0x00000004. It is
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* required to account for changes caused by normal wafer processing
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* parameters."
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*/
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out_be32 (&sdram->sdelay, 0x04);
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return dramsize + dramsize2;
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}
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int checkboard (void)
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{
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puts ("Board: IPEK01 \n");
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return 0;
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}
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void flash_preinit (void)
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{
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struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
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/*
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* Now, when we are in RAM, enable flash write
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* access for detection process.
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* Note that CS_BOOT cannot be cleared when
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* executing in flash.
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*/
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clrbits_be32 (&lpb->cs0_cfg, 0x1); /* clear RO */
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}
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void flash_afterinit (ulong start, ulong size)
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{
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struct mpc5xxx_mmap_ctl *mmap_ctl =
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(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
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#if defined(CONFIG_BOOT_ROM)
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/* adjust mapping */
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out_be32 (&mmap_ctl->cs1_start, START_REG (start));
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out_be32 (&mmap_ctl->cs1_stop, STOP_REG (start, size));
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#else
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/* adjust mapping */
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out_be32 (&mmap_ctl->boot_start, START_REG (start));
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out_be32 (&mmap_ctl->cs0_start, START_REG (start));
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out_be32 (&mmap_ctl->boot_stop, STOP_REG (start, size));
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out_be32 (&mmap_ctl->cs0_stop, STOP_REG (start, size));
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#endif
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}
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extern flash_info_t flash_info[]; /* info for FLASH chips */
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int misc_init_r (void)
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{
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/* adjust flash start */
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gd->bd->bi_flashstart = flash_info[0].start[0];
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return (0);
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}
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#ifdef CONFIG_PCI
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static struct pci_controller hose;
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extern void pci_mpc5xxx_init (struct pci_controller *);
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void pci_init_board (void)
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{
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pci_mpc5xxx_init (&hose);
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}
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#endif
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup (blob, bd);
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fdt_fixup_memory (blob, (u64) bd->bi_memstart, (u64) bd->bi_memsize);
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return 0;
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}
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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int board_eth_init(bd_t *bis)
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{
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cpu_eth_init(bis); /* Built in FEC comes first */
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return pci_eth_init(bis);
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}
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#ifdef CONFIG_VIDEO
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extern GraphicDevice mb862xx;
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static const gdc_regs init_regs[] = {
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{0x0100, 0x00000900},
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{0x0020, 0x80190257},
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{0x0024, 0x00000000},
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{0x0028, 0x00000000},
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{0x002c, 0x00000000},
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{0x0110, 0x00000000},
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{0x0114, 0x00000000},
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{0x0118, 0x02570320},
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{0x0004, 0x041f0000},
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{0x0008, 0x031f031f},
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{0x000c, 0x067f0347},
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{0x0010, 0x02780000},
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{0x0014, 0x0257025c},
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{0x0018, 0x00000000},
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{0x001c, 0x02570320},
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{0x0100, 0x80010900},
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{0x0, 0x0}
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};
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const gdc_regs *board_get_regs (void)
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{
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return init_regs;
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}
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/* Returns Lime base address */
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unsigned int board_video_init (void)
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{
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if (mb862xx_probe (CONFIG_SYS_LIME_BASE) != MB862XX_TYPE_LIME)
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return 0;
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mb862xx.winSizeX = 800;
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mb862xx.winSizeY = 600;
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mb862xx.gdfIndex = GDF_15BIT_555RGB;
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mb862xx.gdfBytesPP = 2;
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return CONFIG_SYS_LIME_BASE;
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}
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#if defined(CONFIG_CONSOLE_EXTRA_INFO)
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/*
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* Return text to be printed besides the logo.
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*/
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void video_get_info_str (int line_number, char *info)
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{
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if (line_number == 1)
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strcpy (info, " Board: IPEK01");
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else
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info[0] = '\0';
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}
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#endif
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#endif /* CONFIG_VIDEO */
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