mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-01 17:10:42 +09:00
f3a8e2b7d4
LS1043ARDB Specification: ------------------------- Memory subsystem: * 2GByte DDR4 SDRAM (32bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * XFI 10G port * QSGMII with 4x 1G ports * Two RGMII ports PCIe: * PCIe2 (Lanes C) to mini-PCIe slot * PCIe3 (Lanes D) to PCIe slot USB 3.0: two super speed USB 3.0 type A ports UART: supports two UARTs up to 115200 bps for console Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
44 lines
1.2 KiB
C
44 lines
1.2 KiB
C
/*
|
|
* Copyright 2015 Freescale Semiconductor
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#ifndef __CPLD_H__
|
|
#define __CPLD_H__
|
|
|
|
/*
|
|
* CPLD register set of LS1043ARDB board-specific.
|
|
*/
|
|
struct cpld_data {
|
|
u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
|
|
u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
|
|
u8 pcba_ver; /* 0x2 - PCBA Revision Register */
|
|
u8 system_rst; /* 0x3 - system reset register */
|
|
u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */
|
|
u8 cfg_rcw_src1; /* 0x5 - Reset config word 1 */
|
|
u8 cfg_rcw_src2; /* 0x6 - Reset config word 1 */
|
|
u8 vbank; /* 0x7 - Flash bank selection Control */
|
|
u8 sysclk_sel; /* 0x8 - */
|
|
u8 uart_sel; /* 0x9 - */
|
|
u8 sd1refclk_sel; /* 0xA - */
|
|
u8 tdmclk_mux_sel; /* 0xB - */
|
|
u8 sdhc_spics_sel; /* 0xC - */
|
|
u8 status_led; /* 0xD - */
|
|
u8 global_rst; /* 0xE - */
|
|
};
|
|
|
|
u8 cpld_read(unsigned int reg);
|
|
void cpld_write(unsigned int reg, u8 value);
|
|
void cpld_rev_bit(unsigned char *value);
|
|
|
|
#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
|
|
#define CPLD_WRITE(reg, value) \
|
|
cpld_write(offsetof(struct cpld_data, reg), value)
|
|
|
|
/* CPLD on IFC */
|
|
#define CPLD_SW_MUX_BANK_SEL 0x40
|
|
#define CPLD_BANK_SEL_MASK 0x07
|
|
#define CPLD_BANK_SEL_ALTBANK 0x04
|
|
#endif
|