mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-10 05:06:16 +09:00
f39748ae8e
- Add support for the Logic Zoom LH7A40x based SDK board(s),
specifically the LPD7A400.
* Patches by Robert Schwebel, 15 May 2004:
- call MAC address reading code also for SMSC91C111;
- make SMSC91C111 timeout configurable, remove duplicate code
- fix get_timer() for PXA
- update doc/README.JFFS2
- use "bootfile" env variable also for jffs2
84 lines
2.2 KiB
C
84 lines
2.2 KiB
C
/*
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* (C) Copyright 2001-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, d.mueller@elsoft.ch
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <lh7a40x.h>
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/* ------------------------------------------------------------------------- */
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/* NOTE: This describes the proper use of this file.
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*
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* CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
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*
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* get_FCLK(), get_HCLK(), get_PCLK() return the clock of
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* the specified bus in HZ.
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*/
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/* ------------------------------------------------------------------------- */
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ulong get_PLLCLK (void)
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{
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return CONFIG_SYS_CLK_FREQ;
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}
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/* return FCLK frequency */
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ulong get_FCLK (void)
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{
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LH7A40X_CSC_PTR (csc);
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ulong maindiv1, maindiv2, prediv, ps;
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/*
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* from userguide 6.1.1.2
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*
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* FCLK = ((MAINDIV1 +2) * (MAINDIV2 +2) * 14.7456MHz) /
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* ((PREDIV+2) * (2^PS))
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*/
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maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11;
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maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7;
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prediv = (csc->clkset & CLKSET_PREDIV) >> 2;
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ps = (csc->clkset & CLKSET_PS) >> 16;
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return (((maindiv2 + 2) * (maindiv1 + 2) * CONFIG_SYS_CLK_FREQ) /
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((prediv + 2) * (1 << ps)));
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}
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/* return HCLK frequency */
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ulong get_HCLK (void)
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{
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LH7A40X_CSC_PTR (csc);
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return (get_FCLK () / ((csc->clkset & CLKSET_HCLKDIV) + 1));
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}
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/* return PCLK frequency */
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ulong get_PCLK (void)
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{
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LH7A40X_CSC_PTR (csc);
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return (get_HCLK () /
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(1 << (((csc->clkset & CLKSET_PCLKDIV) >> 16) + 1)));
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}
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