mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
55 lines
2.1 KiB
C
55 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/**
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* Copyright 2011 Freescale Semiconductor
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* Author: Mingkai Hu <Mingkai.hu@freescale.com>
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*
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* This file provides support for the ngPIXIS, a board-specific FPGA used on
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* some Freescale reference boards.
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*/
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/*
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* CPLD register set. Feel free to add board-specific #ifdefs where necessary.
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*/
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typedef struct cpld_data {
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u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
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u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
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u8 pcba_ver; /* 0x2 - PCBA Revision Register */
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u8 system_rst; /* 0x3 - system reset register */
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u8 res0; /* 0x4 - not used */
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u8 sw_ctl_on; /* 0x5 - Switch Control Enable Register */
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u8 por_cfg; /* 0x6 - POR Control Register */
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u8 switch_strobe; /* 0x7 - Multiplexed pin Select Register */
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u8 jtag_sel; /* 0x8 - JTAG or AURORA Selection */
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u8 sdbank1_clk; /* 0x9 - SerDes Bank1 Reference clock */
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u8 sdbank2_clk; /* 0xa - SerDes Bank2 Reference clock */
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u8 fbank_sel; /* 0xb - Flash bank selection */
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u8 serdes_mux; /* 0xc - Multiplexed pin Select Register */
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u8 sw[1]; /* 0xd - SW2 Status */
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u8 system_rst_default; /* 0xe - system reset to default register */
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u8 sysclk_sw1; /* 0xf - sysclk configuration register */
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} __attribute__ ((packed)) cpld_data_t;
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#define SERDES_MUX_LANE_6_MASK 0x2
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#define SERDES_MUX_LANE_6_SHIFT 1
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#define SERDES_MUX_LANE_A_MASK 0x1
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#define SERDES_MUX_LANE_A_SHIFT 0
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#define SERDES_MUX_LANE_C_MASK 0x4
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#define SERDES_MUX_LANE_C_SHIFT 2
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#define SERDES_MUX_LANE_D_MASK 0x8
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#define SERDES_MUX_LANE_D_SHIFT 3
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#define CPLD_SWITCH_BANK_ENABLE 0x40
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#define CPLD_SYSCLK_83 0x1 /* system clock 83.3MHz */
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#define CPLD_SYSCLK_100 0x2 /* system clock 100MHz */
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/* Pointer to the CPLD register set */
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#define cpld ((cpld_data_t *)CPLD_BASE)
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/* The CPLD SW register that corresponds to board switch X, where x >= 1 */
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#define CPLD_SW(x) (cpld->sw[(x) - 2])
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u8 cpld_read(unsigned int reg);
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void cpld_write(unsigned int reg, u8 value);
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#define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg))
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#define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value)
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