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https://github.com/brain-hackers/u-boot-brain
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2b62997ce9
CPSW is an on-chip ethernet switch that is found on various SoCs from Texas Instruments. This patch adds a simple driver (based on the Linux driver) for this hardware module. This patch also adds support to clean and flush dcache during packet send and receive. Changes by Sandhya: Added support to clean and flush dcache during packet send/receive and added timeouts. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com> [Ilya: Cleaned cache handling, some style cleanup, some small fixes, use of internal RAM for descriptors] Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
52 lines
1.4 KiB
C
52 lines
1.4 KiB
C
/*
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* CPSW Ethernet Switch Driver
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _CPSW_H_
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#define _CPSW_H_
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struct cpsw_slave_data {
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u32 slave_reg_ofs;
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u32 sliver_reg_ofs;
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int phy_id;
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int phy_if;
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};
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enum {
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CPSW_CTRL_VERSION_1 = 0,
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CPSW_CTRL_VERSION_2 /* am33xx like devices */
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};
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struct cpsw_platform_data {
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u32 mdio_base;
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u32 cpsw_base;
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int mdio_div;
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int channels; /* number of cpdma channels (symmetric) */
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u32 cpdma_reg_ofs; /* cpdma register offset */
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int slaves; /* number of slave cpgmac ports */
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u32 ale_reg_ofs; /* address lookup engine reg offset */
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int ale_entries; /* ale table size */
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u32 host_port_reg_ofs; /* cpdma host port registers */
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u32 hw_stats_reg_ofs; /* cpsw hw stats counters */
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u32 mac_control;
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struct cpsw_slave_data *slave_data;
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void (*control)(int enabled);
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u32 host_port_num;
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u8 version;
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};
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int cpsw_register(struct cpsw_platform_data *data);
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#endif /* _CPSW_H_ */
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