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https://github.com/brain-hackers/u-boot-brain
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![Joe Hershberger](/assets/img/avatar_default.png)
Run scripts/coccinelle/net/mdio_register.cocci on the U-Boot code base. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
739 lines
18 KiB
C
739 lines
18 KiB
C
/*
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* (C) Copyright 2011
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* eInfochips Ltd. <www.einfochips.com>
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* Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
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*
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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* Contributor: Mahavir Jain <mjain@marvell.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <net.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/types.h>
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#include <asm/byteorder.h>
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#include <linux/err.h>
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#include <linux/mii.h>
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#include <asm/io.h>
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#include <asm/arch/armada100.h>
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#include "armada100_fec.h"
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#define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */
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#ifdef DEBUG
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static int eth_dump_regs(struct eth_device *dev)
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{
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struct armdfec_device *darmdfec = to_darmdfec(dev);
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struct armdfec_reg *regs = darmdfec->regs;
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unsigned int i = 0;
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printf("\noffset: phy_adr, value: 0x%x\n", readl(®s->phyadr));
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printf("offset: smi, value: 0x%x\n", readl(®s->smi));
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for (i = 0x400; i <= 0x4e4; i += 4)
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printf("offset: 0x%x, value: 0x%x\n",
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i, readl(ARMD1_FEC_BASE + i));
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return 0;
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}
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#endif
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static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond)
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{
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u32 timeout = PHY_WAIT_ITERATIONS;
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u32 reg_val;
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while (--timeout) {
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reg_val = readl(reg);
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if (cond && (reg_val & flag))
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break;
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else if (!cond && !(reg_val & flag))
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break;
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udelay(PHY_WAIT_MICRO_SECONDS);
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}
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return !timeout;
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}
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static int smi_reg_read(struct mii_dev *bus, int phy_addr, int devad,
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int phy_reg)
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{
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u16 value = 0;
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struct eth_device *dev = eth_get_dev_by_name(bus->name);
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struct armdfec_device *darmdfec = to_darmdfec(dev);
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struct armdfec_reg *regs = darmdfec->regs;
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u32 val;
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if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
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val = readl(®s->phyadr);
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value = val & 0x1f;
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return value;
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}
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/* check parameters */
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if (phy_addr > PHY_MASK) {
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printf("ARMD100 FEC: (%s) Invalid phy address: 0x%X\n",
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__func__, phy_addr);
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return -EINVAL;
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}
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if (phy_reg > PHY_MASK) {
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printf("ARMD100 FEC: (%s) Invalid register offset: 0x%X\n",
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__func__, phy_reg);
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return -EINVAL;
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}
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/* wait for the SMI register to become available */
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if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) {
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printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
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return -1;
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}
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writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, ®s->smi);
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/* now wait for the data to be valid */
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if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, true)) {
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val = readl(®s->smi);
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printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n",
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__func__, val);
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return -1;
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}
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val = readl(®s->smi);
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value = val & 0xffff;
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return value;
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}
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static int smi_reg_write(struct mii_dev *bus, int phy_addr, int devad,
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int phy_reg, u16 value)
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{
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struct eth_device *dev = eth_get_dev_by_name(bus->name);
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struct armdfec_device *darmdfec = to_darmdfec(dev);
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struct armdfec_reg *regs = darmdfec->regs;
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if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
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clrsetbits_le32(®s->phyadr, 0x1f, value & 0x1f);
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return 0;
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}
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/* check parameters */
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if (phy_addr > PHY_MASK) {
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printf("ARMD100 FEC: (%s) Invalid phy address\n", __func__);
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return -EINVAL;
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}
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if (phy_reg > PHY_MASK) {
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printf("ARMD100 FEC: (%s) Invalid register offset\n", __func__);
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return -EINVAL;
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}
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/* wait for the SMI register to become available */
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if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) {
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printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
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return -1;
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}
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writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_W | (value & 0xffff),
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®s->smi);
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return 0;
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}
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/*
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* Abort any transmit and receive operations and put DMA
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* in idle state. AT and AR bits are cleared upon entering
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* in IDLE state. So poll those bits to verify operation.
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*/
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static void abortdma(struct eth_device *dev)
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{
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struct armdfec_device *darmdfec = to_darmdfec(dev);
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struct armdfec_reg *regs = darmdfec->regs;
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int delay;
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int maxretries = 40;
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u32 tmp;
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while (--maxretries) {
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writel(SDMA_CMD_AR | SDMA_CMD_AT, ®s->sdma_cmd);
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udelay(100);
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delay = 10;
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while (--delay) {
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tmp = readl(®s->sdma_cmd);
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if (!(tmp & (SDMA_CMD_AR | SDMA_CMD_AT)))
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break;
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udelay(10);
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}
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if (delay)
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break;
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}
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if (!maxretries)
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printf("ARMD100 FEC: (%s) DMA Stuck\n", __func__);
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}
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static inline u32 nibble_swapping_32_bit(u32 x)
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{
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return ((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4);
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}
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static inline u32 nibble_swapping_16_bit(u32 x)
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{
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return ((x & 0x0000f0f0) >> 4) | ((x & 0x00000f0f) << 4);
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}
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static inline u32 flip_4_bits(u32 x)
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{
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return ((x & 0x01) << 3) | ((x & 0x002) << 1)
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| ((x & 0x04) >> 1) | ((x & 0x008) >> 3);
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}
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/*
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* This function will calculate the hash function of the address.
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* depends on the hash mode and hash size.
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* Inputs
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* mach - the 2 most significant bytes of the MAC address.
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* macl - the 4 least significant bytes of the MAC address.
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* Outputs
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* return the calculated entry.
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*/
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static u32 hash_function(u32 mach, u32 macl)
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{
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u32 hashresult;
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u32 addrh;
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u32 addrl;
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u32 addr0;
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u32 addr1;
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u32 addr2;
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u32 addr3;
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u32 addrhswapped;
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u32 addrlswapped;
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addrh = nibble_swapping_16_bit(mach);
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addrl = nibble_swapping_32_bit(macl);
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addrhswapped = flip_4_bits(addrh & 0xf)
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+ ((flip_4_bits((addrh >> 4) & 0xf)) << 4)
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+ ((flip_4_bits((addrh >> 8) & 0xf)) << 8)
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+ ((flip_4_bits((addrh >> 12) & 0xf)) << 12);
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addrlswapped = flip_4_bits(addrl & 0xf)
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+ ((flip_4_bits((addrl >> 4) & 0xf)) << 4)
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+ ((flip_4_bits((addrl >> 8) & 0xf)) << 8)
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+ ((flip_4_bits((addrl >> 12) & 0xf)) << 12)
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+ ((flip_4_bits((addrl >> 16) & 0xf)) << 16)
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+ ((flip_4_bits((addrl >> 20) & 0xf)) << 20)
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+ ((flip_4_bits((addrl >> 24) & 0xf)) << 24)
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+ ((flip_4_bits((addrl >> 28) & 0xf)) << 28);
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addrh = addrhswapped;
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addrl = addrlswapped;
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addr0 = (addrl >> 2) & 0x03f;
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addr1 = (addrl & 0x003) | (((addrl >> 8) & 0x7f) << 2);
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addr2 = (addrl >> 15) & 0x1ff;
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addr3 = ((addrl >> 24) & 0x0ff) | ((addrh & 1) << 8);
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hashresult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
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hashresult = hashresult & 0x07ff;
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return hashresult;
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}
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/*
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* This function will add an entry to the address table.
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* depends on the hash mode and hash size that was initialized.
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* Inputs
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* mach - the 2 most significant bytes of the MAC address.
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* macl - the 4 least significant bytes of the MAC address.
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* skip - if 1, skip this address.
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* rd - the RD field in the address table.
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* Outputs
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* address table entry is added.
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* 0 if success.
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* -ENOSPC if table full
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*/
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static int add_del_hash_entry(struct armdfec_device *darmdfec, u32 mach,
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u32 macl, u32 rd, u32 skip, int del)
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{
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struct addr_table_entry_t *entry, *start;
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u32 newhi;
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u32 newlo;
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u32 i;
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newlo = (((mach >> 4) & 0xf) << 15)
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| (((mach >> 0) & 0xf) << 11)
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| (((mach >> 12) & 0xf) << 7)
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| (((mach >> 8) & 0xf) << 3)
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| (((macl >> 20) & 0x1) << 31)
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| (((macl >> 16) & 0xf) << 27)
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| (((macl >> 28) & 0xf) << 23)
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| (((macl >> 24) & 0xf) << 19)
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| (skip << HTESKIP) | (rd << HTERDBIT)
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| HTEVALID;
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newhi = (((macl >> 4) & 0xf) << 15)
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| (((macl >> 0) & 0xf) << 11)
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| (((macl >> 12) & 0xf) << 7)
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| (((macl >> 8) & 0xf) << 3)
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| (((macl >> 21) & 0x7) << 0);
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/*
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* Pick the appropriate table, start scanning for free/reusable
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* entries at the index obtained by hashing the specified MAC address
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*/
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start = (struct addr_table_entry_t *)(darmdfec->htpr);
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entry = start + hash_function(mach, macl);
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for (i = 0; i < HOP_NUMBER; i++) {
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if (!(entry->lo & HTEVALID)) {
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break;
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} else {
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/* if same address put in same position */
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if (((entry->lo & 0xfffffff8) == (newlo & 0xfffffff8))
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&& (entry->hi == newhi))
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break;
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}
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if (entry == start + 0x7ff)
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entry = start;
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else
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entry++;
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}
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if (((entry->lo & 0xfffffff8) != (newlo & 0xfffffff8)) &&
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(entry->hi != newhi) && del)
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return 0;
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if (i == HOP_NUMBER) {
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if (!del) {
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printf("ARMD100 FEC: (%s) table section is full\n",
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__func__);
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return -ENOSPC;
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} else {
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return 0;
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}
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}
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/*
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* Update the selected entry
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*/
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if (del) {
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entry->hi = 0;
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entry->lo = 0;
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} else {
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entry->hi = newhi;
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entry->lo = newlo;
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}
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return 0;
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}
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/*
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* Create an addressTable entry from MAC address info
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* found in the specifed net_device struct
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*
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* Input : pointer to ethernet interface network device structure
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* Output : N/A
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*/
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static void update_hash_table_mac_address(struct armdfec_device *darmdfec,
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u8 *oaddr, u8 *addr)
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{
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u32 mach;
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u32 macl;
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/* Delete old entry */
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if (oaddr) {
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mach = (oaddr[0] << 8) | oaddr[1];
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macl = (oaddr[2] << 24) | (oaddr[3] << 16) |
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(oaddr[4] << 8) | oaddr[5];
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add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_DELETE);
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}
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/* Add new entry */
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mach = (addr[0] << 8) | addr[1];
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macl = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
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add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_ADD);
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}
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/* Address Table Initialization */
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static void init_hashtable(struct eth_device *dev)
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{
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struct armdfec_device *darmdfec = to_darmdfec(dev);
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struct armdfec_reg *regs = darmdfec->regs;
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memset(darmdfec->htpr, 0, HASH_ADDR_TABLE_SIZE);
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writel((u32)darmdfec->htpr, ®s->htpr);
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}
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/*
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* This detects PHY chip from address 0-31 by reading PHY status
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* registers. PHY chip can be connected at any of this address.
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*/
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static int ethernet_phy_detect(struct eth_device *dev)
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{
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u32 val;
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u16 tmp, mii_status;
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u8 addr;
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for (addr = 0; addr < 32; addr++) {
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if (miiphy_read(dev->name, addr, MII_BMSR, &mii_status) != 0)
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/* try next phy */
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continue;
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/* invalid MII status. More validation required here... */
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if (mii_status == 0 || mii_status == 0xffff)
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/* try next phy */
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continue;
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if (miiphy_read(dev->name, addr, MII_PHYSID1, &tmp) != 0)
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/* try next phy */
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continue;
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val = tmp << 16;
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if (miiphy_read(dev->name, addr, MII_PHYSID2, &tmp) != 0)
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/* try next phy */
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continue;
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val |= tmp;
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if ((val & 0xfffffff0) != 0)
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return addr;
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}
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return -1;
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}
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static void armdfec_init_rx_desc_ring(struct armdfec_device *darmdfec)
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{
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struct rx_desc *p_rx_desc;
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int i;
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/* initialize the Rx descriptors ring */
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p_rx_desc = darmdfec->p_rxdesc;
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for (i = 0; i < RINGSZ; i++) {
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p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
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p_rx_desc->buf_size = PKTSIZE_ALIGN;
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p_rx_desc->byte_cnt = 0;
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p_rx_desc->buf_ptr = darmdfec->p_rxbuf + i * PKTSIZE_ALIGN;
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if (i == (RINGSZ - 1)) {
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p_rx_desc->nxtdesc_p = darmdfec->p_rxdesc;
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} else {
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p_rx_desc->nxtdesc_p = (struct rx_desc *)
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((u32)p_rx_desc + ARMDFEC_RXQ_DESC_ALIGNED_SIZE);
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p_rx_desc = p_rx_desc->nxtdesc_p;
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}
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}
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darmdfec->p_rxdesc_curr = darmdfec->p_rxdesc;
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}
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|
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static int armdfec_init(struct eth_device *dev, bd_t *bd)
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{
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struct armdfec_device *darmdfec = to_darmdfec(dev);
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struct armdfec_reg *regs = darmdfec->regs;
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int phy_adr;
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u32 temp;
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armdfec_init_rx_desc_ring(darmdfec);
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|
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/* Disable interrupts */
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writel(0, ®s->im);
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writel(0, ®s->ic);
|
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/* Write to ICR to clear interrupts. */
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writel(0, ®s->iwc);
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|
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/*
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* Abort any transmit and receive operations and put DMA
|
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* in idle state.
|
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*/
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abortdma(dev);
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/* Initialize address hash table */
|
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init_hashtable(dev);
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|
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/* SDMA configuration */
|
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writel(SDCR_BSZ8 | /* Burst size = 32 bytes */
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SDCR_RIFB | /* Rx interrupt on frame */
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SDCR_BLMT | /* Little endian transmit */
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SDCR_BLMR | /* Little endian receive */
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SDCR_RC_MAX_RETRANS, /* Max retransmit count */
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®s->sdma_conf);
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/* Port Configuration */
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writel(PCR_HS, ®s->pconf); /* Hash size is 1/2kb */
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|
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/* Set extended port configuration */
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writel(PCXR_2BSM | /* Two byte suffix aligns IP hdr */
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PCXR_DSCP_EN | /* Enable DSCP in IP */
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PCXR_MFL_1536 | /* Set MTU = 1536 */
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PCXR_FLP | /* do not force link pass */
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PCXR_TX_HIGH_PRI, /* Transmit - high priority queue */
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®s->pconf_ext);
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|
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update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr);
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|
|
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/* Update TX and RX queue descriptor register */
|
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temp = (u32)®s->txcdp[TXQ];
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writel((u32)darmdfec->p_txdesc, temp);
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temp = (u32)®s->rxfdp[RXQ];
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writel((u32)darmdfec->p_rxdesc, temp);
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temp = (u32)®s->rxcdp[RXQ];
|
|
writel((u32)darmdfec->p_rxdesc_curr, temp);
|
|
|
|
/* Enable Interrupts */
|
|
writel(ALL_INTS, ®s->im);
|
|
|
|
/* Enable Ethernet Port */
|
|
setbits_le32(®s->pconf, PCR_EN);
|
|
|
|
/* Enable RX DMA engine */
|
|
setbits_le32(®s->sdma_cmd, SDMA_CMD_ERD);
|
|
|
|
#ifdef DEBUG
|
|
eth_dump_regs(dev);
|
|
#endif
|
|
|
|
#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
|
|
|
|
#if defined(CONFIG_PHY_BASE_ADR)
|
|
miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, CONFIG_PHY_BASE_ADR);
|
|
#else
|
|
/* Search phy address from range 0-31 */
|
|
phy_adr = ethernet_phy_detect(dev);
|
|
if (phy_adr < 0) {
|
|
printf("ARMD100 FEC: PHY not detected at address range 0-31\n");
|
|
return -1;
|
|
} else {
|
|
debug("ARMD100 FEC: PHY detected at addr %d\n", phy_adr);
|
|
miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, phy_adr);
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
|
|
/* Wait up to 5s for the link status */
|
|
for (i = 0; i < 5; i++) {
|
|
u16 phy_adr;
|
|
|
|
miiphy_read(dev->name, 0xFF, 0xFF, &phy_adr);
|
|
/* Return if we get link up */
|
|
if (miiphy_link(dev->name, phy_adr))
|
|
return 0;
|
|
udelay(1000000);
|
|
}
|
|
|
|
printf("ARMD100 FEC: No link on %s\n", dev->name);
|
|
return -1;
|
|
#endif
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
static void armdfec_halt(struct eth_device *dev)
|
|
{
|
|
struct armdfec_device *darmdfec = to_darmdfec(dev);
|
|
struct armdfec_reg *regs = darmdfec->regs;
|
|
|
|
/* Stop RX DMA */
|
|
clrbits_le32(®s->sdma_cmd, SDMA_CMD_ERD);
|
|
|
|
/*
|
|
* Abort any transmit and receive operations and put DMA
|
|
* in idle state.
|
|
*/
|
|
abortdma(dev);
|
|
|
|
/* Disable interrupts */
|
|
writel(0, ®s->im);
|
|
writel(0, ®s->ic);
|
|
writel(0, ®s->iwc);
|
|
|
|
/* Disable Port */
|
|
clrbits_le32(®s->pconf, PCR_EN);
|
|
}
|
|
|
|
static int armdfec_send(struct eth_device *dev, void *dataptr, int datasize)
|
|
{
|
|
struct armdfec_device *darmdfec = to_darmdfec(dev);
|
|
struct armdfec_reg *regs = darmdfec->regs;
|
|
struct tx_desc *p_txdesc = darmdfec->p_txdesc;
|
|
void *p = (void *)dataptr;
|
|
int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS;
|
|
u32 cmd_sts, temp;
|
|
|
|
/* Copy buffer if it's misaligned */
|
|
if ((u32)dataptr & 0x07) {
|
|
if (datasize > PKTSIZE_ALIGN) {
|
|
printf("ARMD100 FEC: Non-aligned data too large (%d)\n",
|
|
datasize);
|
|
return -1;
|
|
}
|
|
memcpy(darmdfec->p_aligned_txbuf, p, datasize);
|
|
p = darmdfec->p_aligned_txbuf;
|
|
}
|
|
|
|
p_txdesc->cmd_sts = TX_ZERO_PADDING | TX_GEN_CRC;
|
|
p_txdesc->cmd_sts |= TX_FIRST_DESC | TX_LAST_DESC;
|
|
p_txdesc->cmd_sts |= BUF_OWNED_BY_DMA;
|
|
p_txdesc->cmd_sts |= TX_EN_INT;
|
|
p_txdesc->buf_ptr = p;
|
|
p_txdesc->byte_cnt = datasize;
|
|
|
|
/* Apply send command using high priority TX queue */
|
|
temp = (u32)®s->txcdp[TXQ];
|
|
writel((u32)p_txdesc, temp);
|
|
writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, ®s->sdma_cmd);
|
|
|
|
/*
|
|
* wait for packet xmit completion
|
|
*/
|
|
cmd_sts = readl(&p_txdesc->cmd_sts);
|
|
while (cmd_sts & BUF_OWNED_BY_DMA) {
|
|
/* return fail if error is detected */
|
|
if ((cmd_sts & (TX_ERROR | TX_LAST_DESC)) ==
|
|
(TX_ERROR | TX_LAST_DESC)) {
|
|
printf("ARMD100 FEC: (%s) in xmit packet\n", __func__);
|
|
return -1;
|
|
}
|
|
cmd_sts = readl(&p_txdesc->cmd_sts);
|
|
if (!(retry--)) {
|
|
printf("ARMD100 FEC: (%s) xmit packet timeout!\n",
|
|
__func__);
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int armdfec_recv(struct eth_device *dev)
|
|
{
|
|
struct armdfec_device *darmdfec = to_darmdfec(dev);
|
|
struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr;
|
|
u32 cmd_sts;
|
|
u32 timeout = 0;
|
|
u32 temp;
|
|
|
|
/* wait untill rx packet available or timeout */
|
|
do {
|
|
if (timeout < PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS) {
|
|
timeout++;
|
|
} else {
|
|
debug("ARMD100 FEC: %s time out...\n", __func__);
|
|
return -1;
|
|
}
|
|
} while (readl(&p_rxdesc_curr->cmd_sts) & BUF_OWNED_BY_DMA);
|
|
|
|
if (p_rxdesc_curr->byte_cnt != 0) {
|
|
debug("ARMD100 FEC: %s: Received %d byte Packet @ 0x%x"
|
|
"(cmd_sts= %08x)\n", __func__,
|
|
(u32)p_rxdesc_curr->byte_cnt,
|
|
(u32)p_rxdesc_curr->buf_ptr,
|
|
(u32)p_rxdesc_curr->cmd_sts);
|
|
}
|
|
|
|
/*
|
|
* In case received a packet without first/last bits on
|
|
* OR the error summary bit is on,
|
|
* the packets needs to be dropeed.
|
|
*/
|
|
cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
|
|
|
|
if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
|
|
(RX_FIRST_DESC | RX_LAST_DESC)) {
|
|
printf("ARMD100 FEC: (%s) Dropping packet spread on"
|
|
" multiple descriptors\n", __func__);
|
|
} else if (cmd_sts & RX_ERROR) {
|
|
printf("ARMD100 FEC: (%s) Dropping packet with errors\n",
|
|
__func__);
|
|
} else {
|
|
/* !!! call higher layer processing */
|
|
debug("ARMD100 FEC: (%s) Sending Received packet to"
|
|
" upper layer (net_process_received_packet)\n", __func__);
|
|
|
|
/*
|
|
* let the upper layer handle the packet, subtract offset
|
|
* as two dummy bytes are added in received buffer see
|
|
* PORT_CONFIG_EXT register bit TWO_Byte_Stuff_Mode bit.
|
|
*/
|
|
net_process_received_packet(
|
|
p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET,
|
|
(int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
|
|
}
|
|
/*
|
|
* free these descriptors and point next in the ring
|
|
*/
|
|
p_rxdesc_curr->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
|
|
p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
|
|
p_rxdesc_curr->byte_cnt = 0;
|
|
|
|
temp = (u32)&darmdfec->p_rxdesc_curr;
|
|
writel((u32)p_rxdesc_curr->nxtdesc_p, temp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int armada100_fec_register(unsigned long base_addr)
|
|
{
|
|
struct armdfec_device *darmdfec;
|
|
struct eth_device *dev;
|
|
|
|
darmdfec = malloc(sizeof(struct armdfec_device));
|
|
if (!darmdfec)
|
|
goto error;
|
|
|
|
memset(darmdfec, 0, sizeof(struct armdfec_device));
|
|
|
|
darmdfec->htpr = memalign(8, HASH_ADDR_TABLE_SIZE);
|
|
if (!darmdfec->htpr)
|
|
goto error1;
|
|
|
|
darmdfec->p_rxdesc = memalign(PKTALIGN,
|
|
ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1);
|
|
|
|
if (!darmdfec->p_rxdesc)
|
|
goto error1;
|
|
|
|
darmdfec->p_rxbuf = memalign(PKTALIGN, RINGSZ * PKTSIZE_ALIGN + 1);
|
|
if (!darmdfec->p_rxbuf)
|
|
goto error1;
|
|
|
|
darmdfec->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
|
|
if (!darmdfec->p_aligned_txbuf)
|
|
goto error1;
|
|
|
|
darmdfec->p_txdesc = memalign(PKTALIGN, sizeof(struct tx_desc) + 1);
|
|
if (!darmdfec->p_txdesc)
|
|
goto error1;
|
|
|
|
dev = &darmdfec->dev;
|
|
/* Assign ARMADA100 Fast Ethernet Controller Base Address */
|
|
darmdfec->regs = (void *)base_addr;
|
|
|
|
/* must be less than sizeof(dev->name) */
|
|
strcpy(dev->name, "armd-fec0");
|
|
|
|
dev->init = armdfec_init;
|
|
dev->halt = armdfec_halt;
|
|
dev->send = armdfec_send;
|
|
dev->recv = armdfec_recv;
|
|
|
|
eth_register(dev);
|
|
|
|
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
|
|
int retval;
|
|
struct mii_dev *mdiodev = mdio_alloc();
|
|
if (!mdiodev)
|
|
return -ENOMEM;
|
|
strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
|
|
mdiodev->read = smi_reg_read;
|
|
mdiodev->write = smi_reg_write;
|
|
|
|
retval = mdio_register(mdiodev);
|
|
if (retval < 0)
|
|
return retval;
|
|
#endif
|
|
return 0;
|
|
|
|
error1:
|
|
free(darmdfec->p_aligned_txbuf);
|
|
free(darmdfec->p_rxbuf);
|
|
free(darmdfec->p_rxdesc);
|
|
free(darmdfec->htpr);
|
|
error:
|
|
free(darmdfec);
|
|
printf("AMD100 FEC: (%s) Failed to allocate memory\n", __func__);
|
|
return -1;
|
|
}
|