mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-13 22:56:17 +09:00
f32f7fe7bd
The ethernet hang is caused by receiving buffer in DRAM is not yet ready due to access cycles require longer time in DRAM. Relocate DMA buffer descriptors from DRAM to internal SRAM. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
298 lines
8.7 KiB
C
298 lines
8.7 KiB
C
/*
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* Configuation settings for the Freescale MCF5485 FireEngine board.
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*
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* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef _M5485EVB_H
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#define _M5485EVB_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MCF547x_8x /* define processor family */
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#define CONFIG_M548x /* define processor type */
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#define CONFIG_M5485 /* define processor type */
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#define CONFIG_MCFUART
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#define CFG_UART_PORT (0)
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#define CONFIG_BAUDRATE 115200
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#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
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#define CONFIG_HW_WATCHDOG
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#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
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/* Command line configuration */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_CACHE
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#undef CONFIG_CMD_DATE
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_MISC
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_USB
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#define CONFIG_SLTTMR
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#define CONFIG_FSLDMAFEC
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#ifdef CONFIG_FSLDMAFEC
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# define CONFIG_NET_MULTI 1
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# define CONFIG_MII 1
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# define CONFIG_MII_INIT 1
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# define CONFIG_HAS_ETH1
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# define CFG_DMA_USE_INTSRAM 1
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# define CFG_DISCOVER_PHY
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# define CFG_RX_ETH_BUFFER 32
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# define CFG_TX_ETH_BUFFER 48
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# define CFG_FAULT_ECHO_LINK_DOWN
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# define CFG_FEC0_PINMUX 0
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# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
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# define CFG_FEC1_PINMUX 0
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# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE
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# define MCFFEC_TOUT_LOOP 50000
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/* If CFG_DISCOVER_PHY is not defined - hardcoded */
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# ifndef CFG_DISCOVER_PHY
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# define FECDUPLEX FULL
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# define FECSPEED _100BASET
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# else
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# ifndef CFG_FAULT_ECHO_LINK_DOWN
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# define CFG_FAULT_ECHO_LINK_DOWN
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# endif
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# endif /* CFG_DISCOVER_PHY */
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# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
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# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
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# define CONFIG_IPADDR 192.162.1.2
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# define CONFIG_NETMASK 255.255.255.0
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# define CONFIG_SERVERIP 192.162.1.1
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# define CONFIG_GATEWAYIP 192.162.1.1
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# define CONFIG_OVERWRITE_ETHADDR_ONCE
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#endif
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#ifdef CONFIG_CMD_USB
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# define CONFIG_USB_STORAGE
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# define CONFIG_DOS_PARTITION
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# define CONFIG_USB_OHCI_NEW
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# ifndef CONFIG_CMD_PCI
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# define CONFIG_CMD_PCI
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# endif
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/*# define CONFIG_PCI_OHCI*/
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# define CFG_USB_OHCI_REGS_BASE 0x80041000
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# define CFG_USB_OHCI_MAX_ROOT_PORTS 15
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# define CFG_USB_OHCI_SLOT_NAME "isp1561"
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# define CFG_OHCI_SWAP_REG_ACCESS
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#endif
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/* I2C */
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#define CONFIG_FSL_I2C
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#define CONFIG_HARD_I2C /* I2C with hw support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 80000
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_OFFSET 0x00008F00
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#define CFG_IMMR CFG_MBAR
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/* PCI */
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#ifdef CONFIG_CMD_PCI
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#define CONFIG_PCI 1
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#define CONFIG_PCI_PNP 1
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#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
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#define CFG_PCI_MEM_BUS 0x80000000
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#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS
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#define CFG_PCI_MEM_SIZE 0x10000000
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#define CFG_PCI_IO_BUS 0x71000000
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#define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS
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#define CFG_PCI_IO_SIZE 0x01000000
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#define CFG_PCI_CFG_BUS 0x70000000
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#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS
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#define CFG_PCI_CFG_SIZE 0x01000000
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#endif
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#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
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#define CONFIG_UDP_CHECKSUM
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#define CONFIG_HOSTNAME M548xEVB
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"loadaddr=10000\0" \
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"u-boot=u-boot.bin\0" \
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"load=tftp ${loadaddr) ${u-boot}\0" \
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"upd=run load; run prog\0" \
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"prog=prot off bank 1;" \
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"era ff800000 ff82ffff;" \
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"cp.b ${loadaddr} ff800000 ${filesize};"\
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"save\0" \
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""
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#define CONFIG_PRAM 512 /* 512 KB */
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#define CFG_PROMPT "-> "
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#define CFG_LONGHELP /* undef to save memory */
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#ifdef CONFIG_CMD_KGDB
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# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_LOAD_ADDR 0x00010000
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#define CFG_HZ 1000
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#define CFG_CLK CFG_BUSCLK
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#define CFG_CPU_CLK CFG_CLK * 2
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#define CFG_MBAR 0xF0000000
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#define CFG_INTSRAM (CFG_MBAR + 0x10000)
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#define CFG_INTSRAMSZ 0x8000
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/*#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)*/
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR 0xF2000000
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#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
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#define CFG_INIT_RAM_CTRL 0x21
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#define CFG_INIT_RAM1_ADDR (CFG_INIT_RAM_ADDR + CFG_INIT_RAM_END)
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#define CFG_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
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#define CFG_INIT_RAM1_CTRL 0x21
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_SDRAM_CFG1 0x73711630
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#define CFG_SDRAM_CFG2 0x46370000
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#define CFG_SDRAM_CTRL 0xE10B0000
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#define CFG_SDRAM_EMOD 0x40010000
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#define CFG_SDRAM_MODE 0x018D0000
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#define CFG_SDRAM_DRVSTRENGTH 0x000002AA
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#ifdef CFG_DRAMSZ1
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# define CFG_SDRAM_SIZE (CFG_DRAMSZ + CFG_DRAMSZ1)
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#else
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# define CFG_SDRAM_SIZE CFG_DRAMSZ
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#endif
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#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
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#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
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#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_BOOTPARAMS_LEN 64*1024
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization ??
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*/
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#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_FLASH_CFI
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#ifdef CFG_FLASH_CFI
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# define CFG_FLASH_BASE (CFG_CS0_BASE)
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# define CFG_FLASH_CFI_DRIVER 1
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# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
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# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
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# define CFG_FLASH_USE_BUFFER_WRITE
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#ifdef CFG_NOR1SZ
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# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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# define CFG_FLASH_SIZE ((CFG_NOR1SZ + CFG_BOOTSZ) << 20)
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# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE }
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#else
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# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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# define CFG_FLASH_SIZE (CFG_BOOTSZ << 20)
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#endif
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#endif
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/* Configuration for environment
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* Environment is embedded in u-boot in the second sector of the flash
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*/
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#define CFG_ENV_OFFSET 0x2000
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#define CFG_ENV_SECT_SIZE 0x2000
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_IS_EMBEDDED 1
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16
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/*-----------------------------------------------------------------------
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* Chipselect bank definitions
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*/
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/*
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* CS0 - NOR Flash 1, 2, 4, or 8MB
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* CS1 - NOR Flash
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* CS2 - Available
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* CS3 - Available
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* CS4 - Available
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* CS5 - Available
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*/
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#define CFG_CS0_BASE 0xFF800000
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#define CFG_CS0_MASK (((CFG_BOOTSZ << 20) - 1) & 0xFFFF0001)
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#define CFG_CS0_CTRL 0x00101980
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#ifdef CFG_NOR1SZ
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#define CFG_CS1_BASE 0xF8000000
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#define CFG_CS1_MASK (((CFG_NOR1SZ << 20) - 1) & 0xFFFF0001)
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#define CFG_CS1_CTRL 0x00000D80
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#endif
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#endif /* _M5485EVB_H */
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