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![Sylwester Nawrocki](/assets/img/avatar_default.png)
This patch adds basic driver PCI Express controller found on Broadcom set-top-box SoCs, e.g. BCM2711. The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI handling removed. The inbound access memory region is not currently parsed from dma-ranges DT property and a fixed 3GB region is used. The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805 USB Host Controller. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
624 lines
18 KiB
C
624 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Broadcom STB PCIe controller driver
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*
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* Copyright (C) 2020 Samsung Electronics Co., Ltd.
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*
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* Based on upstream Linux kernel driver:
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* drivers/pci/controller/pcie-brcmstb.c
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* Copyright (C) 2009 - 2017 Broadcom
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*
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* Based driver by Nicolas Saenz Julienne
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* Copyright (C) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
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*/
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#include <common.h>
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#include <errno.h>
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#include <dm.h>
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#include <dm/ofnode.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <linux/bitfield.h>
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#include <linux/log2.h>
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#include <linux/iopoll.h>
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/* Offset of the mandatory PCIe capability config registers */
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#define BRCM_PCIE_CAP_REGS 0x00ac
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/* The PCIe controller register offsets */
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#define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1 0x0188
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#define VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
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#define VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0
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#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
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#define CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
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#define PCIE_RC_DL_MDIO_ADDR 0x1100
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#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
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#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
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#define PCIE_MISC_MISC_CTRL 0x4008
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#define MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
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#define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
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#define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
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#define MISC_CTRL_MAX_BURST_SIZE_128 0x0
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#define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
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#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
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#define PCIE_MEM_WIN0_LO(win) \
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PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
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#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
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#define PCIE_MEM_WIN0_HI(win) \
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PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
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#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
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#define RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
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#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
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#define RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
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#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
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#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
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#define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
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#define PCIE_MISC_PCIE_STATUS 0x4068
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#define STATUS_PCIE_PORT_MASK 0x80
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#define STATUS_PCIE_PORT_SHIFT 7
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#define STATUS_PCIE_DL_ACTIVE_MASK 0x20
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#define STATUS_PCIE_DL_ACTIVE_SHIFT 5
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#define STATUS_PCIE_PHYLINKUP_MASK 0x10
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#define STATUS_PCIE_PHYLINKUP_SHIFT 4
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#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
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#define MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
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#define MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
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#define MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12
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#define PCIE_MEM_WIN0_BASE_LIMIT(win) \
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PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
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#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
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#define MEM_WIN0_BASE_HI_BASE_MASK 0xff
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#define PCIE_MEM_WIN0_BASE_HI(win) \
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PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
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#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
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#define PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
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#define PCIE_MEM_WIN0_LIMIT_HI(win) \
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PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
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#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
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#define PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
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#define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
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#define PCIE_MSI_INTR2_CLR 0x4508
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#define PCIE_MSI_INTR2_MASK_SET 0x4510
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#define PCIE_EXT_CFG_DATA 0x8000
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#define PCIE_EXT_CFG_INDEX 0x9000
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#define PCIE_EXT_BUSNUM_SHIFT 20
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#define PCIE_EXT_SLOT_SHIFT 15
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#define PCIE_EXT_FUNC_SHIFT 12
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#define PCIE_RGR1_SW_INIT_1 0x9210
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#define RGR1_SW_INIT_1_PERST_MASK 0x1
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#define RGR1_SW_INIT_1_INIT_MASK 0x2
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/* PCIe parameters */
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#define BRCM_NUM_PCIE_OUT_WINS 4
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/* MDIO registers */
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#define MDIO_PORT0 0x0
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#define MDIO_DATA_MASK 0x7fffffff
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#define MDIO_DATA_SHIFT 0
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#define MDIO_PORT_MASK 0xf0000
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#define MDIO_PORT_SHIFT 16
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#define MDIO_REGAD_MASK 0xffff
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#define MDIO_REGAD_SHIFT 0
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#define MDIO_CMD_MASK 0xfff00000
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#define MDIO_CMD_SHIFT 20
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#define MDIO_CMD_READ 0x1
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#define MDIO_CMD_WRITE 0x0
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#define MDIO_DATA_DONE_MASK 0x80000000
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#define SSC_REGS_ADDR 0x1100
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#define SET_ADDR_OFFSET 0x1f
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#define SSC_CNTL_OFFSET 0x2
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#define SSC_CNTL_OVRD_EN_MASK 0x8000
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#define SSC_CNTL_OVRD_VAL_MASK 0x4000
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#define SSC_STATUS_OFFSET 0x1
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#define SSC_STATUS_SSC_MASK 0x400
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#define SSC_STATUS_SSC_SHIFT 10
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#define SSC_STATUS_PLL_LOCK_MASK 0x800
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#define SSC_STATUS_PLL_LOCK_SHIFT 11
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/**
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* struct brcm_pcie - the PCIe controller state
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* @base: Base address of memory mapped IO registers of the controller
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* @gen: Non-zero value indicates limitation of the PCIe controller operation
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* to a specific generation (1, 2 or 3)
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* @ssc: true indicates active Spread Spectrum Clocking operation
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*/
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struct brcm_pcie {
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void __iomem *base;
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int gen;
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bool ssc;
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};
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/**
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* brcm_pcie_encode_ibar_size() - Encode the inbound "BAR" region size
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* @size: The inbound region size
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*
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* This function converts size of the inbound "BAR" region to the non-linear
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* values of the PCIE_MISC_RC_BAR[123]_CONFIG_LO register SIZE field.
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*
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* Return: The encoded inbound region size
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*/
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static int brcm_pcie_encode_ibar_size(u64 size)
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{
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int log2_in = ilog2(size);
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if (log2_in >= 12 && log2_in <= 15)
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/* Covers 4KB to 32KB (inclusive) */
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return (log2_in - 12) + 0x1c;
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else if (log2_in >= 16 && log2_in <= 37)
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/* Covers 64KB to 32GB, (inclusive) */
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return log2_in - 15;
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/* Something is awry so disable */
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return 0;
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}
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/**
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* brcm_pcie_rc_mode() - Check if PCIe controller is in RC mode
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* @pcie: Pointer to the PCIe controller state
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*
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* The controller is capable of serving in both RC and EP roles.
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*
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* Return: true for RC mode, false for EP mode.
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*/
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static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
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{
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u32 val;
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val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
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return (val & STATUS_PCIE_PORT_MASK) >> STATUS_PCIE_PORT_SHIFT;
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}
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/**
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* brcm_pcie_link_up() - Check whether the PCIe link is up
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* @pcie: Pointer to the PCIe controller state
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*
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* Return: true if the link is up, false otherwise.
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*/
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static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
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{
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u32 val, dla, plu;
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val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
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dla = (val & STATUS_PCIE_DL_ACTIVE_MASK) >> STATUS_PCIE_DL_ACTIVE_SHIFT;
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plu = (val & STATUS_PCIE_PHYLINKUP_MASK) >> STATUS_PCIE_PHYLINKUP_SHIFT;
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return dla && plu;
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}
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static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf,
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uint offset, void **paddress)
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{
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struct brcm_pcie *pcie = dev_get_priv(dev);
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unsigned int pci_bus = PCI_BUS(bdf);
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unsigned int pci_dev = PCI_DEV(bdf);
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unsigned int pci_func = PCI_FUNC(bdf);
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int idx;
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/*
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* Busses 0 (host PCIe bridge) and 1 (its immediate child)
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* are limited to a single device each
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*/
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if (pci_bus < 2 && pci_dev > 0)
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return -EINVAL;
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/* Accesses to the RC go right to the RC registers */
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if (pci_bus == 0) {
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*paddress = pcie->base + offset;
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return 0;
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}
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/* For devices, write to the config space index register */
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idx = (pci_bus << PCIE_EXT_BUSNUM_SHIFT)
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| (pci_dev << PCIE_EXT_SLOT_SHIFT)
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| (pci_func << PCIE_EXT_FUNC_SHIFT);
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writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
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*paddress = pcie->base + PCIE_EXT_CFG_DATA + offset;
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return 0;
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}
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static int brcm_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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return pci_generic_mmap_read_config(bus, brcm_pcie_config_address,
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bdf, offset, valuep, size);
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}
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static int brcm_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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return pci_generic_mmap_write_config(bus, brcm_pcie_config_address,
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bdf, offset, value, size);
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}
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static const char *link_speed_to_str(unsigned int cls)
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{
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switch (cls) {
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case PCI_EXP_LNKSTA_CLS_2_5GB: return "2.5";
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case PCI_EXP_LNKSTA_CLS_5_0GB: return "5.0";
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case PCI_EXP_LNKSTA_CLS_8_0GB: return "8.0";
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default:
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break;
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}
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return "??";
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}
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static u32 brcm_pcie_mdio_form_pkt(unsigned int port, unsigned int regad,
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unsigned int cmd)
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{
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u32 pkt;
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pkt = (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
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pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
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pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
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return pkt;
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}
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/**
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* brcm_pcie_mdio_read() - Perform a register read on the internal MDIO bus
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* @base: Pointer to the PCIe controller IO registers
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* @port: The MDIO port number
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* @regad: The register address
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* @val: A pointer at which to store the read value
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*
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* Return: 0 on success and register value in @val, negative error value
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* on failure.
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*/
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static int brcm_pcie_mdio_read(void __iomem *base, unsigned int port,
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unsigned int regad, u32 *val)
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{
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u32 data, addr;
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int ret;
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addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ);
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writel(addr, base + PCIE_RC_DL_MDIO_ADDR);
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readl(base + PCIE_RC_DL_MDIO_ADDR);
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ret = readl_poll_timeout(base + PCIE_RC_DL_MDIO_RD_DATA, data,
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(data & MDIO_DATA_DONE_MASK), 100);
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*val = data & MDIO_DATA_MASK;
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return ret;
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}
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/**
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* brcm_pcie_mdio_write() - Perform a register write on the internal MDIO bus
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* @base: Pointer to the PCIe controller IO registers
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* @port: The MDIO port number
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* @regad: Address of the register
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* @wrdata: The value to write
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*
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* Return: 0 on success, negative error value on failure.
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*/
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static int brcm_pcie_mdio_write(void __iomem *base, unsigned int port,
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unsigned int regad, u16 wrdata)
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{
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u32 data, addr;
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addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE);
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writel(addr, base + PCIE_RC_DL_MDIO_ADDR);
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readl(base + PCIE_RC_DL_MDIO_ADDR);
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writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
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return readl_poll_timeout(base + PCIE_RC_DL_MDIO_WR_DATA, data,
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!(data & MDIO_DATA_DONE_MASK), 100);
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}
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/**
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* brcm_pcie_set_ssc() - Configure the controller for Spread Spectrum Clocking
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* @base: pointer to the PCIe controller IO registers
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*
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* Return: 0 on success, negative error value on failure.
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*/
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static int brcm_pcie_set_ssc(void __iomem *base)
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{
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int pll, ssc;
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int ret;
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u32 tmp;
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ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET,
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SSC_REGS_ADDR);
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if (ret < 0)
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return ret;
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ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp);
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if (ret < 0)
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return ret;
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tmp |= (SSC_CNTL_OVRD_EN_MASK | SSC_CNTL_OVRD_VAL_MASK);
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ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp);
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if (ret < 0)
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return ret;
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udelay(1000);
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ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp);
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if (ret < 0)
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return ret;
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ssc = (tmp & SSC_STATUS_SSC_MASK) >> SSC_STATUS_SSC_SHIFT;
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pll = (tmp & SSC_STATUS_PLL_LOCK_MASK) >> SSC_STATUS_PLL_LOCK_SHIFT;
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return ssc && pll ? 0 : -EIO;
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}
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/**
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* brcm_pcie_set_gen() - Limits operation to a specific generation (1, 2 or 3)
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* @pcie: pointer to the PCIe controller state
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* @gen: PCIe generation to limit the controller's operation to
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*/
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static void brcm_pcie_set_gen(struct brcm_pcie *pcie, unsigned int gen)
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{
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void __iomem *cap_base = pcie->base + BRCM_PCIE_CAP_REGS;
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u16 lnkctl2 = readw(cap_base + PCI_EXP_LNKCTL2);
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u32 lnkcap = readl(cap_base + PCI_EXP_LNKCAP);
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lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
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writel(lnkcap, cap_base + PCI_EXP_LNKCAP);
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lnkctl2 = (lnkctl2 & ~0xf) | gen;
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writew(lnkctl2, cap_base + PCI_EXP_LNKCTL2);
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}
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static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
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unsigned int win, u64 phys_addr,
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u64 pcie_addr, u64 size)
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{
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void __iomem *base = pcie->base;
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u32 phys_addr_mb_high, limit_addr_mb_high;
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phys_addr_t phys_addr_mb, limit_addr_mb;
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int high_addr_shift;
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u32 tmp;
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/* Set the base of the pcie_addr window */
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writel(lower_32_bits(pcie_addr), base + PCIE_MEM_WIN0_LO(win));
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writel(upper_32_bits(pcie_addr), base + PCIE_MEM_WIN0_HI(win));
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/* Write the addr base & limit lower bits (in MBs) */
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phys_addr_mb = phys_addr / SZ_1M;
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limit_addr_mb = (phys_addr + size - 1) / SZ_1M;
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tmp = readl(base + PCIE_MEM_WIN0_BASE_LIMIT(win));
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u32p_replace_bits(&tmp, phys_addr_mb,
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MEM_WIN0_BASE_LIMIT_BASE_MASK);
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u32p_replace_bits(&tmp, limit_addr_mb,
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MEM_WIN0_BASE_LIMIT_LIMIT_MASK);
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writel(tmp, base + PCIE_MEM_WIN0_BASE_LIMIT(win));
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/* Write the cpu & limit addr upper bits */
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high_addr_shift = MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT;
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phys_addr_mb_high = phys_addr_mb >> high_addr_shift;
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tmp = readl(base + PCIE_MEM_WIN0_BASE_HI(win));
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u32p_replace_bits(&tmp, phys_addr_mb_high,
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MEM_WIN0_BASE_HI_BASE_MASK);
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writel(tmp, base + PCIE_MEM_WIN0_BASE_HI(win));
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limit_addr_mb_high = limit_addr_mb >> high_addr_shift;
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tmp = readl(base + PCIE_MEM_WIN0_LIMIT_HI(win));
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u32p_replace_bits(&tmp, limit_addr_mb_high,
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PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK);
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writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win));
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}
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static int brcm_pcie_probe(struct udevice *dev)
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{
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struct udevice *ctlr = pci_get_controller(dev);
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struct pci_controller *hose = dev_get_uclass_priv(ctlr);
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struct brcm_pcie *pcie = dev_get_priv(dev);
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void __iomem *base = pcie->base;
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bool ssc_good = false;
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int num_out_wins = 0;
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u64 rc_bar2_offset, rc_bar2_size;
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unsigned int scb_size_val;
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int i, ret;
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u16 nlw, cls, lnksta;
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u32 tmp;
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/*
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* Reset the bridge, assert the fundamental reset. Note for some SoCs,
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* e.g. BCM7278, the fundamental reset should not be asserted here.
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* This will need to be changed when support for other SoCs is added.
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*/
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setbits_le32(base + PCIE_RGR1_SW_INIT_1,
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RGR1_SW_INIT_1_INIT_MASK | RGR1_SW_INIT_1_PERST_MASK);
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/*
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* The delay is a safety precaution to preclude the reset signal
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* from looking like a glitch.
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*/
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udelay(100);
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/* Take the bridge out of reset */
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clrbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK);
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clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
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PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
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/* Wait for SerDes to be stable */
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udelay(100);
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/* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
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clrsetbits_le32(base + PCIE_MISC_MISC_CTRL,
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MISC_CTRL_MAX_BURST_SIZE_MASK,
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MISC_CTRL_SCB_ACCESS_EN_MASK |
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MISC_CTRL_CFG_READ_UR_MODE_MASK |
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MISC_CTRL_MAX_BURST_SIZE_128);
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/*
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* TODO: When support for other SoCs than BCM2711 is added we may
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* need to use the base address and size(s) provided in the dma-ranges
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* property.
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*/
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rc_bar2_offset = 0;
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rc_bar2_size = 0xc0000000;
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tmp = lower_32_bits(rc_bar2_offset);
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u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),
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RC_BAR2_CONFIG_LO_SIZE_MASK);
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writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
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writel(upper_32_bits(rc_bar2_offset),
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base + PCIE_MISC_RC_BAR2_CONFIG_HI);
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scb_size_val = rc_bar2_size ?
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ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
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tmp = readl(base + PCIE_MISC_MISC_CTRL);
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u32p_replace_bits(&tmp, scb_size_val,
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MISC_CTRL_SCB0_SIZE_MASK);
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writel(tmp, base + PCIE_MISC_MISC_CTRL);
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/* Disable the PCIe->GISB memory window (RC_BAR1) */
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clrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO,
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RC_BAR1_CONFIG_LO_SIZE_MASK);
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/* Disable the PCIe->SCB memory window (RC_BAR3) */
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clrbits_le32(base + PCIE_MISC_RC_BAR3_CONFIG_LO,
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RC_BAR3_CONFIG_LO_SIZE_MASK);
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/* Mask all interrupts since we are not handling any yet */
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writel(0xffffffff, base + PCIE_MSI_INTR2_MASK_SET);
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/* Clear any interrupts we find on boot */
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writel(0xffffffff, base + PCIE_MSI_INTR2_CLR);
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if (pcie->gen)
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brcm_pcie_set_gen(pcie, pcie->gen);
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/* Unassert the fundamental reset */
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clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1,
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RGR1_SW_INIT_1_PERST_MASK);
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/* Give the RC/EP time to wake up, before trying to configure RC.
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* Intermittently check status for link-up, up to a total of 100ms.
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*/
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for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
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mdelay(5);
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if (!brcm_pcie_link_up(pcie)) {
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printf("PCIe BRCM: link down\n");
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return -EINVAL;
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}
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if (!brcm_pcie_rc_mode(pcie)) {
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printf("PCIe misconfigured; is in EP mode\n");
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return -EINVAL;
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}
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for (i = 0; i < hose->region_count; i++) {
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struct pci_region *reg = &hose->regions[i];
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if (reg->flags != PCI_REGION_MEM)
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continue;
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if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS)
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return -EINVAL;
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brcm_pcie_set_outbound_win(pcie, num_out_wins, reg->phys_start,
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reg->bus_start, reg->size);
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num_out_wins++;
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}
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/*
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* For config space accesses on the RC, show the right class for
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* a PCIe-PCIe bridge (the default setting is to be EP mode).
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*/
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clrsetbits_le32(base + PCIE_RC_CFG_PRIV1_ID_VAL3,
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CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK, 0x060400);
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if (pcie->ssc) {
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ret = brcm_pcie_set_ssc(pcie->base);
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if (!ret)
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ssc_good = true;
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else
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printf("PCIe BRCM: failed attempt to enter SSC mode\n");
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}
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lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
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cls = lnksta & PCI_EXP_LNKSTA_CLS;
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nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
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printf("PCIe BRCM: link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
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nlw, ssc_good ? "(SSC)" : "(!SSC)");
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/* PCIe->SCB endian mode for BAR */
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clrsetbits_le32(base + PCIE_RC_CFG_VENDOR_SPECIFIC_REG1,
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VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK,
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VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN);
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/*
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* Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
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* is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
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*/
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setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
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PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK);
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return 0;
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}
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static int brcm_pcie_ofdata_to_platdata(struct udevice *dev)
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{
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struct brcm_pcie *pcie = dev_get_priv(dev);
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ofnode dn = dev_ofnode(dev);
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u32 max_link_speed;
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int ret;
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/* Get the controller base address */
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pcie->base = dev_read_addr_ptr(dev);
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if (!pcie->base)
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return -EINVAL;
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pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc");
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ret = ofnode_read_u32(dn, "max-link-speed", &max_link_speed);
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if (ret < 0 || max_link_speed > 4)
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pcie->gen = 0;
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else
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pcie->gen = max_link_speed;
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return 0;
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}
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static const struct dm_pci_ops brcm_pcie_ops = {
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.read_config = brcm_pcie_read_config,
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.write_config = brcm_pcie_write_config,
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};
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static const struct udevice_id brcm_pcie_ids[] = {
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{ .compatible = "brcm,bcm2711-pcie" },
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{ }
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};
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U_BOOT_DRIVER(pcie_brcm_base) = {
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.name = "pcie_brcm",
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.id = UCLASS_PCI,
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.ops = &brcm_pcie_ops,
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.of_match = brcm_pcie_ids,
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.probe = brcm_pcie_probe,
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.ofdata_to_platdata = brcm_pcie_ofdata_to_platdata,
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.priv_auto_alloc_size = sizeof(struct brcm_pcie),
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};
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