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![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
448 lines
9.8 KiB
C
448 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015
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* Cristian Birsan <cristian.birsan@microchip.com>
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* Purna Chandra Mandal <purna.mandal@microchip.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <fdt_support.h>
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#include <flash.h>
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#include <init.h>
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#include <irq_func.h>
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#include <linux/bitops.h>
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#include <mach/pic32.h>
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#include <wait_bit.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* NVM Controller registers */
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struct pic32_reg_nvm {
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struct pic32_reg_atomic ctrl;
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struct pic32_reg_atomic key;
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struct pic32_reg_atomic addr;
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struct pic32_reg_atomic data;
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};
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/* NVM operations */
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#define NVMOP_NOP 0
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#define NVMOP_WORD_WRITE 1
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#define NVMOP_PAGE_ERASE 4
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/* NVM control bits */
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#define NVM_WR BIT(15)
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#define NVM_WREN BIT(14)
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#define NVM_WRERR BIT(13)
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#define NVM_LVDERR BIT(12)
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/* NVM programming unlock register */
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#define LOCK_KEY 0x0
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#define UNLOCK_KEY1 0xaa996655
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#define UNLOCK_KEY2 0x556699aa
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/*
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* PIC32 flash banks consist of number of pages, each page
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* into number of rows and rows into number of words.
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* Here we will maintain page information instead of sector.
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*/
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
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static struct pic32_reg_nvm *nvm_regs_p;
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static inline void flash_initiate_operation(u32 nvmop)
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{
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/* set operation */
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writel(nvmop, &nvm_regs_p->ctrl.raw);
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/* enable flash write */
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writel(NVM_WREN, &nvm_regs_p->ctrl.set);
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/* unlock sequence */
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writel(LOCK_KEY, &nvm_regs_p->key.raw);
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writel(UNLOCK_KEY1, &nvm_regs_p->key.raw);
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writel(UNLOCK_KEY2, &nvm_regs_p->key.raw);
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/* initiate operation */
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writel(NVM_WR, &nvm_regs_p->ctrl.set);
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}
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static int flash_wait_till_busy(const char *func, ulong timeout)
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{
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int ret = wait_for_bit_le32(&nvm_regs_p->ctrl.raw,
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NVM_WR, false, timeout, false);
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return ret ? ERR_TIMEOUT : ERR_OK;
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}
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static inline int flash_complete_operation(void)
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{
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u32 tmp;
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tmp = readl(&nvm_regs_p->ctrl.raw);
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if (tmp & NVM_WRERR) {
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printf("Error in Block Erase - Lock Bit may be set!\n");
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flash_initiate_operation(NVMOP_NOP);
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return ERR_PROTECTED;
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}
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if (tmp & NVM_LVDERR) {
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printf("Error in Block Erase - low-vol detected!\n");
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flash_initiate_operation(NVMOP_NOP);
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return ERR_NOT_ERASED;
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}
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/* disable flash write or erase operation */
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writel(NVM_WREN, &nvm_regs_p->ctrl.clr);
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return ERR_OK;
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}
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/*
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* Erase flash sectors, returns:
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* ERR_OK - OK
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* ERR_INVAL - invalid sector arguments
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* ERR_TIMEOUT - write timeout
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* ERR_NOT_ERASED - Flash not erased
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* ERR_UNKNOWN_FLASH_VENDOR - incorrect flash
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*/
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int flash_erase(flash_info_t *info, int s_first, int s_last)
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{
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ulong sect_start, sect_end, flags;
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int prot, sect;
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int rc;
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if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MCHP) {
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printf("Can't erase unknown flash type %08lx - aborted\n",
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info->flash_id);
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return ERR_UNKNOWN_FLASH_VENDOR;
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}
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if ((s_first < 0) || (s_first > s_last)) {
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printf("- no sectors to erase\n");
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return ERR_INVAL;
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}
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prot = 0;
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for (sect = s_first; sect <= s_last; ++sect) {
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if (info->protect[sect])
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prot++;
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}
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if (prot)
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printf("- Warning: %d protected sectors will not be erased!\n",
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prot);
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else
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printf("\n");
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/* erase on unprotected sectors */
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for (sect = s_first; sect <= s_last; sect++) {
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if (info->protect[sect])
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continue;
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/* disable interrupts */
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flags = disable_interrupts();
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/* write destination page address (physical) */
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sect_start = CPHYSADDR(info->start[sect]);
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writel(sect_start, &nvm_regs_p->addr.raw);
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/* page erase */
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flash_initiate_operation(NVMOP_PAGE_ERASE);
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/* wait */
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rc = flash_wait_till_busy(__func__,
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CONFIG_SYS_FLASH_ERASE_TOUT);
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/* re-enable interrupts if necessary */
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if (flags)
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enable_interrupts();
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if (rc != ERR_OK)
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return rc;
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rc = flash_complete_operation();
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if (rc != ERR_OK)
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return rc;
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/*
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* flash content is updated but cache might contain stale
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* data, so invalidate dcache.
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*/
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sect_end = info->start[sect] + info->size / info->sector_count;
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invalidate_dcache_range(info->start[sect], sect_end);
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}
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printf(" done\n");
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return ERR_OK;
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}
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int page_erase(flash_info_t *info, int sect)
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{
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return 0;
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}
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/* Write a word to flash */
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static int write_word(flash_info_t *info, ulong dest, ulong word)
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{
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ulong flags;
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int rc;
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/* read flash to check if it is sufficiently erased */
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if ((readl((void __iomem *)dest) & word) != word) {
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printf("Error, Flash not erased!\n");
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return ERR_NOT_ERASED;
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}
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/* disable interrupts */
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flags = disable_interrupts();
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/* update destination page address (physical) */
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writel(CPHYSADDR(dest), &nvm_regs_p->addr.raw);
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writel(word, &nvm_regs_p->data.raw);
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/* word write */
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flash_initiate_operation(NVMOP_WORD_WRITE);
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/* wait for operation to complete */
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rc = flash_wait_till_busy(__func__, CONFIG_SYS_FLASH_WRITE_TOUT);
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/* re-enable interrupts if necessary */
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if (flags)
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enable_interrupts();
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if (rc != ERR_OK)
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return rc;
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return flash_complete_operation();
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}
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/*
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* Copy memory to flash, returns:
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* ERR_OK - OK
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* ERR_TIMEOUT - write timeout
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* ERR_NOT_ERASED - Flash not erased
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*/
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int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
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{
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ulong dst, tmp_le, len = cnt;
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int i, l, rc;
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uchar *cp;
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/* get lower word aligned address */
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dst = (addr & ~3);
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/* handle unaligned start bytes */
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l = addr - dst;
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if (l != 0) {
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tmp_le = 0;
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for (i = 0, cp = (uchar *)dst; i < l; ++i, ++cp)
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tmp_le |= *cp << (i * 8);
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for (; (i < 4) && (cnt > 0); ++i, ++src, --cnt, ++cp)
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tmp_le |= *src << (i * 8);
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for (; (cnt == 0) && (i < 4); ++i, ++cp)
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tmp_le |= *cp << (i * 8);
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rc = write_word(info, dst, tmp_le);
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if (rc)
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goto out;
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dst += 4;
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}
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/* handle word aligned part */
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while (cnt >= 4) {
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tmp_le = src[0] | src[1] << 8 | src[2] << 16 | src[3] << 24;
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rc = write_word(info, dst, tmp_le);
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if (rc)
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goto out;
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src += 4;
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dst += 4;
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cnt -= 4;
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}
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if (cnt == 0) {
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rc = ERR_OK;
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goto out;
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}
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/* handle unaligned tail bytes */
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tmp_le = 0;
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for (i = 0, cp = (uchar *)dst; (i < 4) && (cnt > 0); ++i, ++cp) {
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tmp_le |= *src++ << (i * 8);
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--cnt;
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}
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for (; i < 4; ++i, ++cp)
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tmp_le |= *cp << (i * 8);
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rc = write_word(info, dst, tmp_le);
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out:
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/*
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* flash content updated by nvm controller but CPU cache might
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* have stale data, so invalidate dcache.
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*/
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invalidate_dcache_range(addr, addr + len);
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printf(" done\n");
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return rc;
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}
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void flash_print_info(flash_info_t *info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_MCHP:
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printf("Microchip Technology ");
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break;
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default:
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printf("Unknown Vendor ");
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break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_MCHP100T:
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printf("Internal (8 Mbit, 64 x 16k)\n");
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break;
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default:
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printf("Unknown Chip Type\n");
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break;
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}
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printf(" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf(" Sector Start Addresses:");
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for (i = 0; i < info->sector_count; ++i) {
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if ((i % 5) == 0)
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printf("\n ");
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printf(" %08lX%s", info->start[i],
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info->protect[i] ? " (RO)" : " ");
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}
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printf("\n");
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}
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unsigned long flash_init(void)
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{
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unsigned long size = 0;
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struct udevice *dev;
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int bank;
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/* probe every MTD device */
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for (uclass_first_device(UCLASS_MTD, &dev); dev;
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uclass_next_device(&dev)) {
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/* nop */
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}
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/* calc total flash size */
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for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank)
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size += flash_info[bank].size;
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return size;
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}
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static void pic32_flash_bank_init(flash_info_t *info,
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ulong base, ulong size)
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{
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ulong sect_size;
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int sect;
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/* device & manufacturer code */
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info->flash_id = FLASH_MAN_MCHP | FLASH_MCHP100T;
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info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
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info->size = size;
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/* update sector (i.e page) info */
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sect_size = info->size / info->sector_count;
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for (sect = 0; sect < info->sector_count; sect++) {
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info->start[sect] = base;
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/* protect each sector by default */
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info->protect[sect] = 1;
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base += sect_size;
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}
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}
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static int pic32_flash_probe(struct udevice *dev)
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{
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void *blob = (void *)gd->fdt_blob;
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int node = dev_of_offset(dev);
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const char *list, *end;
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const fdt32_t *cell;
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unsigned long addr, size;
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int parent, addrc, sizec;
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flash_info_t *info;
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int len, idx;
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/*
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* decode regs. there are multiple reg tuples, and they need to
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* match with reg-names.
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*/
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parent = fdt_parent_offset(blob, node);
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fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
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list = fdt_getprop(blob, node, "reg-names", &len);
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if (!list)
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return -ENOENT;
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end = list + len;
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cell = fdt_getprop(blob, node, "reg", &len);
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if (!cell)
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return -ENOENT;
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for (idx = 0, info = &flash_info[0]; list < end;) {
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addr = fdt_translate_address((void *)blob, node, cell + idx);
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size = fdt_addr_to_cpu(cell[idx + addrc]);
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len = strlen(list);
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if (!strncmp(list, "nvm", len)) {
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/* NVM controller */
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nvm_regs_p = ioremap(addr, size);
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} else if (!strncmp(list, "bank", 4)) {
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/* Flash bank: use kseg0 cached address */
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pic32_flash_bank_init(info, CKSEG0ADDR(addr), size);
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info++;
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}
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idx += addrc + sizec;
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list += len + 1;
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}
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/* disable flash write/erase operations */
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writel(NVM_WREN, &nvm_regs_p->ctrl.clr);
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#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
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/* monitor protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CONFIG_SYS_MONITOR_BASE,
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CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
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&flash_info[0]);
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#endif
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#ifdef CONFIG_ENV_IS_IN_FLASH
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/* ENV protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR,
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CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
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&flash_info[0]);
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#endif
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return 0;
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}
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static const struct udevice_id pic32_flash_ids[] = {
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{ .compatible = "microchip,pic32mzda-flash" },
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{}
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};
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U_BOOT_DRIVER(pic32_flash) = {
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.name = "pic32_flash",
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.id = UCLASS_MTD,
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.of_match = pic32_flash_ids,
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.probe = pic32_flash_probe,
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};
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