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![Suneel Garapati](/assets/img/avatar_default.png)
Adds support for MMC controllers found on OcteonTX or OcteonTX2 SoC platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Peng Fan <peng.fan@nxp.com>
208 lines
5.5 KiB
C
208 lines
5.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2019 Marvell International Ltd.
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*
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* https://spdx.org/licenses
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*/
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#ifndef __OCTEONTX_HSMMC_H__
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#define __OCTEONTX_HSMMC_H__
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#include <asm/gpio.h>
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/** Name of our driver */
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#define OCTEONTX_MMC_DRIVER_NAME "octeontx-hsmmc"
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/** Maximum supported MMC slots */
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#define OCTEONTX_MAX_MMC_SLOT 3
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#define POWER_ON_TIME 40 /** See SD 4.1 spec figure 6-5 */
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/**
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* Timeout used when waiting for commands to complete. We need to keep this
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* above the hardware watchdog timeout which is usually limited to 1000ms
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*/
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#define WATCHDOG_COUNT (1100) /* in msecs */
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/**
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* Long timeout for commands which might take a while to complete.
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*/
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#define MMC_TIMEOUT_LONG 1000
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/**
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* Short timeout used for most commands in msecs
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*/
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#define MMC_TIMEOUT_SHORT 20
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#define NSEC_PER_SEC 1000000000L
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#define MAX_NO_OF_TAPS 64
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#define EXT_CSD_POWER_CLASS 187 /* R/W */
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/* default HS400 tuning block number */
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#define DEFAULT_HS400_TUNING_BLOCK 1
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struct octeontx_mmc_host;
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/** MMC/SD slot data structure */
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struct octeontx_mmc_slot {
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struct mmc mmc;
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struct mmc_config cfg;
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struct octeontx_mmc_host *host;
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struct udevice *dev;
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void *base_addr; /** Same as host base_addr */
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u64 clock;
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int bus_id; /** slot number */
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uint bus_width;
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uint max_width;
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int hs200_tap_adj;
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int hs400_tap_adj;
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int hs400_tuning_block;
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struct gpio_desc cd_gpio;
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struct gpio_desc wp_gpio;
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struct gpio_desc power_gpio;
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enum bus_mode mode;
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union mio_emm_switch cached_switch;
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union mio_emm_switch want_switch;
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union mio_emm_rca cached_rca;
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union mio_emm_timing taps; /* otx2: MIO_EMM_TIMING */
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union mio_emm_timing hs200_taps;
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union mio_emm_timing hs400_taps;
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/* These are used to see if our tuning is still valid or not */
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enum bus_mode last_mode;
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u32 last_clock;
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u32 block_len;
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u32 block_count;
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int cmd_clk_skew;
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int dat_clk_skew;
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uint cmd_cnt; /* otx: sample cmd in delay */
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uint dat_cnt; /* otx: sample data in delay */
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uint drive; /* Current drive */
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uint slew; /* clock skew */
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uint cmd_out_hs200_delay;
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uint data_out_hs200_delay;
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uint cmd_out_hs400_delay;
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uint data_out_hs400_delay;
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uint clk_period;
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bool valid:1;
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bool is_acmd:1;
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bool tuned:1;
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bool hs200_tuned:1;
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bool hs400_tuned:1;
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bool is_1_8v:1;
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bool is_3_3v:1;
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bool is_ddr:1;
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bool is_asim:1;
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bool is_emul:1;
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bool cd_inverted:1;
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bool wp_inverted:1;
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bool disable_ddr:1;
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bool non_removable:1;
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};
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struct octeontx_mmc_cr_mods {
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u8 ctype_xor;
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u8 rtype_xor;
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};
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struct octeontx_mmc_cr {
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u8 c;
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u8 r;
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};
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struct octeontx_sd_mods {
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struct octeontx_mmc_cr mmc;
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struct octeontx_mmc_cr sd;
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struct octeontx_mmc_cr sdacmd;
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};
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/** Host controller data structure */
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struct octeontx_mmc_host {
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struct udevice *dev;
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void *base_addr;
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struct octeontx_mmc_slot slots[OCTEONTX_MAX_MMC_SLOT + 1];
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pci_dev_t pdev;
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u64 sys_freq;
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union mio_emm_cfg emm_cfg;
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u64 timing_taps;
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struct mmc *last_mmc; /** Last mmc used */
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ofnode node;
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int cur_slotid;
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int last_slotid;
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int max_width;
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uint per_tap_delay;
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uint num_slots;
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uint dma_wait_delay; /* Delay before polling DMA in usecs */
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bool initialized:1;
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bool timing_calibrated:1;
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bool is_asim:1;
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bool is_emul:1;
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bool calibrate_glitch:1;
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bool cond_clock_glitch:1;
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bool tap_requires_noclk:1;
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bool hs400_skew_needed:1;
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};
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/*
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* NOTE: This was copied from the Linux kernel.
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*
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* MMC status in R1, for native mode (SPI bits are different)
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* Type
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* e:error bit
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* s:status bit
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* r:detected and set for the actual command response
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* x:detected and set during command execution. the host must poll
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* the card by sending status command in order to read these bits.
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* Clear condition
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* a:according to the card state
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* b:always related to the previous command. Reception of
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* a valid command will clear it (with a delay of one command)
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* c:clear by read
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*/
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#define R1_OUT_OF_RANGE BIT(31) /* er, c */
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#define R1_ADDRESS_ERROR BIT(30) /* erx, c */
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#define R1_BLOCK_LEN_ERROR BIT(29) /* er, c */
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#define R1_ERASE_SEQ_ERROR BIT(28) /* er, c */
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#define R1_ERASE_PARAM BIT(27) /* ex, c */
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#define R1_WP_VIOLATION BIT(26) /* erx, c */
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#define R1_CARD_IS_LOCKED BIT(25) /* sx, a */
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#define R1_LOCK_UNLOCK_FAILED BIT(24) /* erx, c */
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#define R1_COM_CRC_ERROR BIT(23) /* er, b */
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/*#define R1_ILLEGAL_COMMAND BIT(22)*/ /* er, b */
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#define R1_CARD_ECC_FAILED BIT(21) /* ex, c */
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#define R1_CC_ERROR BIT(20) /* erx, c */
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#define R1_ERROR BIT(19) /* erx, c */
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#define R1_UNDERRUN BIT(18) /* ex, c */
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#define R1_OVERRUN BIT(17) /* ex, c */
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#define R1_CID_CSD_OVERWRITE BIT(16) /* erx, c, CID/CSD overwrite */
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#define R1_WP_ERASE_SKIP BIT(15) /* sx, c */
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#define R1_CARD_ECC_DISABLED BIT(14) /* sx, a */
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#define R1_ERASE_RESET BIT(13) /* sr, c */
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#define R1_STATUS(x) ((x) & 0xFFFFE000)
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#define R1_CURRENT_STATE(x) (((x) & 0x00001E00) >> 9) /* sx, b (4 bits) */
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#define R1_READY_FOR_DATA BIT(8) /* sx, a */
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#define R1_SWITCH_ERROR BIT(7) /* sx, c */
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#define R1_BLOCK_READ_MASK R1_OUT_OF_RANGE | \
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R1_ADDRESS_ERROR | \
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R1_BLOCK_LEN_ERROR | \
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R1_CARD_IS_LOCKED | \
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R1_COM_CRC_ERROR | \
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R1_ILLEGAL_COMMAND | \
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R1_CARD_ECC_FAILED | \
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R1_CC_ERROR | \
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R1_ERROR
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#define R1_BLOCK_WRITE_MASK R1_OUT_OF_RANGE | \
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R1_ADDRESS_ERROR | \
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R1_BLOCK_LEN_ERROR | \
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R1_WP_VIOLATION | \
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R1_CARD_IS_LOCKED | \
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R1_COM_CRC_ERROR | \
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R1_ILLEGAL_COMMAND | \
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R1_CARD_ECC_FAILED | \
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R1_CC_ERROR | \
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R1_ERROR | \
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R1_UNDERRUN | \
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R1_OVERRUN
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#endif /* __OCTEONTX_HSMMC_H__ */
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