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https://github.com/brain-hackers/u-boot-brain
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8c33ba7b1d
On popular request this now completes the Warren's work started for
TK1:
aeb3fcb359
ARM: tegra: Use mem size from MC rather than ODMDATA
In addition to the move of using the Tegra memory controller (MC)
register rather than ODMDATA for T20, T30 and T114 as well it further
uses the generic get_ram_size() function (see "common/memsize.c")
<supposed to be used in each and every U-Boot port>TM. Added benefit is
that it should <catch 99% of hardware related (i. e. reliably
reproducible) memory errors> as well.
Thoroughly tested on the various Toradex line of Tegra modules
available which unfortunately does not include T114 and T124 (yet at
least) plus on the Jetson TK1.
Based-on-work-by: Stephen Warren <swarren@nvidia.com>
Based-on-work-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
36 lines
1.2 KiB
C
36 lines
1.2 KiB
C
/*
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* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _TEGRA114_H_
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#define _TEGRA114_H_
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#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */
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#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
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#define NV_PA_MC_BASE 0x70019000
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#include <asm/arch-tegra/tegra.h>
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#define BCT_ODMDATA_OFFSET 1752 /* offset to ODMDATA word */
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#undef NVBOOTINFOTABLE_BCTSIZE
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#undef NVBOOTINFOTABLE_BCTPTR
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#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */
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#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */
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#define MAX_NUM_CPU 4
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#endif /* TEGRA114_H */
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