mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-31 14:28:52 +09:00
695 lines
17 KiB
C
695 lines
17 KiB
C
/*
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* (C) Copyright 2005-2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#if 0
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#define DEBUG /* define for debug output */
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#endif
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#include <config.h>
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#include <common.h>
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#include <net.h>
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#include <miiphy.h>
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#include <malloc.h>
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#include <asm/processor.h>
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#include <asm/arch-ixp/ixp425.h>
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#include <IxOsal.h>
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#include <IxEthAcc.h>
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#include <IxEthDB.h>
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#include <IxNpeDl.h>
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#include <IxQMgr.h>
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#include <IxNpeMh.h>
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#include <ix_ossl.h>
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#include <IxFeatureCtrl.h>
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#include <npe.h>
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#ifdef CONFIG_IXP4XX_NPE
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static IxQMgrDispatcherFuncPtr qDispatcherFunc = NULL;
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static int npe_exists[NPE_NUM_PORTS];
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static int npe_used[NPE_NUM_PORTS];
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/* A little extra so we can align to cacheline. */
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static u8 npe_alloc_pool[NPE_MEM_POOL_SIZE + CFG_CACHELINE_SIZE - 1];
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static u8 *npe_alloc_end;
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static u8 *npe_alloc_free;
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static void *npe_alloc(int size)
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{
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static int count = 0;
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void *p = NULL;
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size = (size + (CFG_CACHELINE_SIZE-1)) & ~(CFG_CACHELINE_SIZE-1);
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count++;
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if ((npe_alloc_free + size) < npe_alloc_end) {
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p = npe_alloc_free;
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npe_alloc_free += size;
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} else {
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printf("%s: failed (count=%d, size=%d)!\n", count, size);
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}
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return p;
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}
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/* Not interrupt safe! */
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static void mbuf_enqueue(IX_OSAL_MBUF **q, IX_OSAL_MBUF *new)
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{
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IX_OSAL_MBUF *m = *q;
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IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(new) = NULL;
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if (m) {
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while(IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m))
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m = IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m);
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IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m) = new;
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} else
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*q = new;
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}
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/* Not interrupt safe! */
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static IX_OSAL_MBUF *mbuf_dequeue(IX_OSAL_MBUF **q)
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{
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IX_OSAL_MBUF *m = *q;
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if (m)
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*q = IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m);
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return m;
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}
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static void reset_tx_mbufs(struct npe* p_npe)
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{
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IX_OSAL_MBUF *m;
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int i;
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p_npe->txQHead = NULL;
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for (i = 0; i < CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS; i++) {
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m = &p_npe->tx_mbufs[i];
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memset(m, 0, sizeof(*m));
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IX_OSAL_MBUF_MDATA(m) = (void *)&p_npe->tx_pkts[i * NPE_PKT_SIZE];
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IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE;
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mbuf_enqueue(&p_npe->txQHead, m);
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}
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}
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static void reset_rx_mbufs(struct npe* p_npe)
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{
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IX_OSAL_MBUF *m;
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int i;
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p_npe->rxQHead = NULL;
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HAL_DCACHE_INVALIDATE(p_npe->rx_pkts, NPE_PKT_SIZE *
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CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS);
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for (i = 0; i < CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS; i++) {
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m = &p_npe->rx_mbufs[i];
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memset(m, 0, sizeof(*m));
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IX_OSAL_MBUF_MDATA(m) = (void *)&p_npe->rx_pkts[i * NPE_PKT_SIZE];
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IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE;
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if(ixEthAccPortRxFreeReplenish(p_npe->eth_id, m) != IX_SUCCESS) {
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printf("ixEthAccPortRxFreeReplenish failed for port %d\n", p_npe->eth_id);
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break;
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}
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}
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}
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static void init_rx_mbufs(struct npe* p_npe)
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{
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p_npe->rxQHead = NULL;
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p_npe->rx_pkts = npe_alloc(NPE_PKT_SIZE *
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CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS);
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if (p_npe->rx_pkts == NULL) {
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printf("alloc of packets failed.\n");
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return;
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}
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p_npe->rx_mbufs = (IX_OSAL_MBUF *)
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npe_alloc(sizeof(IX_OSAL_MBUF) *
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CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS);
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if (p_npe->rx_mbufs == NULL) {
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printf("alloc of mbufs failed.\n");
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return;
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}
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reset_rx_mbufs(p_npe);
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}
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static void init_tx_mbufs(struct npe* p_npe)
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{
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p_npe->tx_pkts = npe_alloc(NPE_PKT_SIZE *
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CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS);
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if (p_npe->tx_pkts == NULL) {
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printf("alloc of packets failed.\n");
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return;
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}
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p_npe->tx_mbufs = (IX_OSAL_MBUF *)
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npe_alloc(sizeof(IX_OSAL_MBUF) *
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CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS);
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if (p_npe->tx_mbufs == NULL) {
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printf("alloc of mbufs failed.\n");
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return;
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}
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reset_tx_mbufs(p_npe);
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}
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/* Convert IX_ETH_PORT_n to IX_NPEMH_NPEID_NPEx */
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static int __eth_to_npe(int eth_id)
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{
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switch(eth_id) {
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case IX_ETH_PORT_1:
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return IX_NPEMH_NPEID_NPEB;
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case IX_ETH_PORT_2:
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return IX_NPEMH_NPEID_NPEC;
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case IX_ETH_PORT_3:
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return IX_NPEMH_NPEID_NPEA;
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}
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return 0;
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}
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/* Poll the CSR machinery. */
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static void npe_poll(int eth_id)
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{
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if (qDispatcherFunc != NULL) {
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ixNpeMhMessagesReceive(__eth_to_npe(eth_id));
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(*qDispatcherFunc)(IX_QMGR_QUELOW_GROUP);
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}
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}
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/* ethAcc RX callback */
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static void npe_rx_callback(u32 cbTag, IX_OSAL_MBUF *m, IxEthAccPortId portid)
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{
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struct npe* p_npe = (struct npe *)cbTag;
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if (IX_OSAL_MBUF_MLEN(m) > 0) {
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mbuf_enqueue(&p_npe->rxQHead, m);
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if (p_npe->rx_write == ((p_npe->rx_read-1) & (PKTBUFSRX-1))) {
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debug("Rx overflow: rx_write=%d rx_read=%d\n",
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p_npe->rx_write, p_npe->rx_read);
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} else {
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debug("Received message #%d (len=%d)\n", p_npe->rx_write,
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IX_OSAL_MBUF_MLEN(m));
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memcpy((void *)NetRxPackets[p_npe->rx_write], IX_OSAL_MBUF_MDATA(m),
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IX_OSAL_MBUF_MLEN(m));
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p_npe->rx_len[p_npe->rx_write] = IX_OSAL_MBUF_MLEN(m);
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p_npe->rx_write++;
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if (p_npe->rx_write == PKTBUFSRX)
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p_npe->rx_write = 0;
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#ifdef CONFIG_PRINT_RX_FRAMES
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{
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u8 *ptr = IX_OSAL_MBUF_MDATA(m);
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int i;
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for (i=0; i<60; i++) {
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debug("%02x ", *ptr++);
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}
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debug("\n");
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}
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#endif
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}
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m = mbuf_dequeue(&p_npe->rxQHead);
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} else {
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debug("Received frame with length 0!!!\n");
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m = mbuf_dequeue(&p_npe->rxQHead);
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}
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/* Now return mbuf to NPE */
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IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE;
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IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m) = NULL;
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IX_OSAL_MBUF_FLAGS(m) = 0;
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if(ixEthAccPortRxFreeReplenish(p_npe->eth_id, m) != IX_SUCCESS) {
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debug("npe_rx_callback: Error returning mbuf.\n");
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}
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}
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/* ethAcc TX callback */
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static void npe_tx_callback(u32 cbTag, IX_OSAL_MBUF *m)
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{
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struct npe* p_npe = (struct npe *)cbTag;
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debug("%s\n", __FUNCTION__);
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IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE;
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IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m) = NULL;
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IX_OSAL_MBUF_FLAGS(m) = 0;
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mbuf_enqueue(&p_npe->txQHead, m);
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}
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static int npe_set_mac_address(struct eth_device *dev)
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{
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struct npe *p_npe = (struct npe *)dev->priv;
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IxEthAccMacAddr npeMac;
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debug("%s\n", __FUNCTION__);
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/* Set MAC address */
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memcpy(npeMac.macAddress, dev->enetaddr, 6);
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if (ixEthAccPortUnicastMacAddressSet(p_npe->eth_id, &npeMac) != IX_ETH_ACC_SUCCESS) {
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printf("Error setting unicast address! %02x:%02x:%02x:%02x:%02x:%02x\n",
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npeMac.macAddress[0], npeMac.macAddress[1],
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npeMac.macAddress[2], npeMac.macAddress[3],
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npeMac.macAddress[4], npeMac.macAddress[5]);
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return 0;
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}
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return 1;
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}
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/* Boot-time CSR library initialization. */
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static int npe_csr_load(void)
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{
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int i;
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if (ixQMgrInit() != IX_SUCCESS) {
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debug("Error initialising queue manager!\n");
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return 0;
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}
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ixQMgrDispatcherLoopGet(&qDispatcherFunc);
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if(ixNpeMhInitialize(IX_NPEMH_NPEINTERRUPTS_YES) != IX_SUCCESS) {
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printf("Error initialising NPE Message handler!\n");
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return 0;
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}
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if (npe_used[IX_ETH_PORT_1] && npe_exists[IX_ETH_PORT_1] &&
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ixNpeDlNpeInitAndStart(IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS)
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!= IX_SUCCESS) {
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printf("Error downloading firmware to NPE-B!\n");
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return 0;
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}
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if (npe_used[IX_ETH_PORT_2] && npe_exists[IX_ETH_PORT_2] &&
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ixNpeDlNpeInitAndStart(IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS)
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!= IX_SUCCESS) {
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printf("Error downloading firmware to NPE-C!\n");
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return 0;
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}
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/* don't need this for U-Boot */
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ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, FALSE);
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if (ixEthAccInit() != IX_ETH_ACC_SUCCESS) {
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printf("Error initialising Ethernet access driver!\n");
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return 0;
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}
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for (i = 0; i < IX_ETH_ACC_NUMBER_OF_PORTS; i++) {
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if (!npe_used[i] || !npe_exists[i])
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continue;
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if (ixEthAccPortInit(i) != IX_ETH_ACC_SUCCESS) {
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printf("Error initialising Ethernet port%d!\n", i);
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}
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if (ixEthAccTxSchedulingDisciplineSet(i, FIFO_NO_PRIORITY) != IX_ETH_ACC_SUCCESS) {
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printf("Error setting scheduling discipline for port %d.\n", i);
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}
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if (ixEthAccPortRxFrameAppendFCSDisable(i) != IX_ETH_ACC_SUCCESS) {
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printf("Error disabling RX FCS for port %d.\n", i);
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}
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if (ixEthAccPortTxFrameAppendFCSEnable(i) != IX_ETH_ACC_SUCCESS) {
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printf("Error enabling TX FCS for port %d.\n", i);
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}
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}
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return 1;
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}
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static int npe_init(struct eth_device *dev, bd_t * bis)
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{
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struct npe *p_npe = (struct npe *)dev->priv;
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int i;
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u16 reg_short;
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int speed;
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int duplex;
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debug("%s: 1\n", __FUNCTION__);
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miiphy_read (dev->name, p_npe->phy_no, PHY_BMSR, ®_short);
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/*
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* Wait if PHY is capable of autonegotiation and autonegotiation is not complete
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*/
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if ((reg_short & PHY_BMSR_AUTN_ABLE) && !(reg_short & PHY_BMSR_AUTN_COMP)) {
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puts ("Waiting for PHY auto negotiation to complete");
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i = 0;
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while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
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/*
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* Timeout reached ?
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*/
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if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
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puts (" TIMEOUT !\n");
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break;
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}
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if ((i++ % 1000) == 0) {
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putc ('.');
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miiphy_read (dev->name, p_npe->phy_no, PHY_BMSR, ®_short);
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}
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udelay (1000); /* 1 ms */
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}
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puts (" done\n");
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udelay (500000); /* another 500 ms (results in faster booting) */
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}
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speed = miiphy_speed (dev->name, p_npe->phy_no);
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duplex = miiphy_duplex (dev->name, p_npe->phy_no);
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if (p_npe->print_speed) {
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p_npe->print_speed = 0;
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printf ("ENET Speed is %d Mbps - %s duplex connection\n",
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(int) speed, (duplex == HALF) ? "HALF" : "FULL");
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}
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npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool);
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npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool +
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CFG_CACHELINE_SIZE - 1) & ~(CFG_CACHELINE_SIZE - 1));
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/* initialize mbuf pool */
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init_rx_mbufs(p_npe);
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init_tx_mbufs(p_npe);
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if (ixEthAccPortRxCallbackRegister(p_npe->eth_id, npe_rx_callback,
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(u32)p_npe) != IX_ETH_ACC_SUCCESS) {
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printf("can't register RX callback!\n");
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return 0;
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}
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if (ixEthAccPortTxDoneCallbackRegister(p_npe->eth_id, npe_tx_callback,
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(u32)p_npe) != IX_ETH_ACC_SUCCESS) {
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printf("can't register TX callback!\n");
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return 0;
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}
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npe_set_mac_address(dev);
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if (ixEthAccPortEnable(p_npe->eth_id) != IX_ETH_ACC_SUCCESS) {
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printf("can't enable port!\n");
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return 0;
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}
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p_npe->active = 1;
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return 1;
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}
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#if 0 /* test-only: probably have to deal with it when booting linux (for a clean state) */
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/* Uninitialize CSR library. */
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static void npe_csr_unload(void)
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{
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ixEthAccUnload();
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ixEthDBUnload();
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ixNpeMhUnload();
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ixQMgrUnload();
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}
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/* callback which is used by ethAcc to recover RX buffers when stopping */
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static void npe_rx_stop_callback(u32 cbTag, IX_OSAL_MBUF *m, IxEthAccPortId portid)
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{
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debug("%s\n", __FUNCTION__);
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}
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/* callback which is used by ethAcc to recover TX buffers when stopping */
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static void npe_tx_stop_callback(u32 cbTag, IX_OSAL_MBUF *m)
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{
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debug("%s\n", __FUNCTION__);
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}
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#endif
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static void npe_halt(struct eth_device *dev)
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{
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struct npe *p_npe = (struct npe *)dev->priv;
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int i;
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debug("%s\n", __FUNCTION__);
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/* Delay to give time for recovery of mbufs */
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for (i = 0; i < 100; i++) {
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npe_poll(p_npe->eth_id);
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udelay(100);
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}
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#if 0 /* test-only: probably have to deal with it when booting linux (for a clean state) */
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if (ixEthAccPortRxCallbackRegister(p_npe->eth_id, npe_rx_stop_callback,
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(u32)p_npe) != IX_ETH_ACC_SUCCESS) {
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debug("Error registering rx callback!\n");
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}
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if (ixEthAccPortTxDoneCallbackRegister(p_npe->eth_id, npe_tx_stop_callback,
|
|
(u32)p_npe) != IX_ETH_ACC_SUCCESS) {
|
|
debug("Error registering tx callback!\n");
|
|
}
|
|
|
|
if (ixEthAccPortDisable(p_npe->eth_id) != IX_ETH_ACC_SUCCESS) {
|
|
debug("npe_stop: Error disabling NPEB!\n");
|
|
}
|
|
|
|
/* Delay to give time for recovery of mbufs */
|
|
for (i = 0; i < 100; i++) {
|
|
npe_poll(p_npe->eth_id);
|
|
udelay(10000);
|
|
}
|
|
|
|
/*
|
|
* For U-Boot only, we are probably launching Linux or other OS that
|
|
* needs a clean slate for its NPE library.
|
|
*/
|
|
#if 0 /* test-only */
|
|
for (i = 0; i < IX_ETH_ACC_NUMBER_OF_PORTS; i++) {
|
|
if (npe_used[i] && npe_exists[i])
|
|
if (ixNpeDlNpeStopAndReset(__eth_to_npe(i)) != IX_SUCCESS)
|
|
printf("Failed to stop and reset NPE B.\n");
|
|
}
|
|
#endif
|
|
|
|
#endif
|
|
p_npe->active = 0;
|
|
}
|
|
|
|
|
|
static int npe_send(struct eth_device *dev, volatile void *packet, int len)
|
|
{
|
|
struct npe *p_npe = (struct npe *)dev->priv;
|
|
u8 *dest;
|
|
int err;
|
|
IX_OSAL_MBUF *m;
|
|
|
|
debug("%s\n", __FUNCTION__);
|
|
m = mbuf_dequeue(&p_npe->txQHead);
|
|
dest = IX_OSAL_MBUF_MDATA(m);
|
|
IX_OSAL_MBUF_PKT_LEN(m) = IX_OSAL_MBUF_MLEN(m) = len;
|
|
IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m) = NULL;
|
|
|
|
memcpy(dest, (char *)packet, len);
|
|
|
|
if ((err = ixEthAccPortTxFrameSubmit(p_npe->eth_id, m, IX_ETH_ACC_TX_DEFAULT_PRIORITY))
|
|
!= IX_ETH_ACC_SUCCESS) {
|
|
printf("npe_send: Can't submit frame. err[%d]\n", err);
|
|
mbuf_enqueue(&p_npe->txQHead, m);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef DEBUG_PRINT_TX_FRAMES
|
|
{
|
|
u8 *ptr = IX_OSAL_MBUF_MDATA(m);
|
|
int i;
|
|
|
|
for (i=0; i<IX_OSAL_MBUF_MLEN(m); i++) {
|
|
printf("%02x ", *ptr++);
|
|
}
|
|
printf(" (tx-len=%d)\n", IX_OSAL_MBUF_MLEN(m));
|
|
}
|
|
#endif
|
|
|
|
npe_poll(p_npe->eth_id);
|
|
|
|
return len;
|
|
}
|
|
|
|
static int npe_rx(struct eth_device *dev)
|
|
{
|
|
struct npe *p_npe = (struct npe *)dev->priv;
|
|
|
|
debug("%s\n", __FUNCTION__);
|
|
npe_poll(p_npe->eth_id);
|
|
|
|
debug("%s: rx_write=%d rx_read=%d\n", __FUNCTION__, p_npe->rx_write, p_npe->rx_read);
|
|
while (p_npe->rx_write != p_npe->rx_read) {
|
|
debug("Reading message #%d\n", p_npe->rx_read);
|
|
NetReceive(NetRxPackets[p_npe->rx_read], p_npe->rx_len[p_npe->rx_read]);
|
|
p_npe->rx_read++;
|
|
if (p_npe->rx_read == PKTBUFSRX)
|
|
p_npe->rx_read = 0;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int npe_initialize(bd_t * bis)
|
|
{
|
|
static int virgin = 0;
|
|
struct eth_device *dev;
|
|
int eth_num = 0;
|
|
struct npe *p_npe = NULL;
|
|
|
|
for (eth_num = 0; eth_num < CFG_NPE_NUMS; eth_num++) {
|
|
|
|
/* See if we can actually bring up the interface, otherwise, skip it */
|
|
switch (eth_num) {
|
|
default: /* fall through */
|
|
case 0:
|
|
if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
|
|
continue;
|
|
}
|
|
break;
|
|
#ifdef CONFIG_HAS_ETH1
|
|
case 1:
|
|
if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
|
|
continue;
|
|
}
|
|
break;
|
|
#endif
|
|
}
|
|
|
|
/* Allocate device structure */
|
|
dev = (struct eth_device *)malloc(sizeof(*dev));
|
|
if (dev == NULL) {
|
|
printf ("%s: Cannot allocate eth_device %d\n", __FUNCTION__, eth_num);
|
|
return -1;
|
|
}
|
|
memset(dev, 0, sizeof(*dev));
|
|
|
|
/* Allocate our private use data */
|
|
p_npe = (struct npe *)malloc(sizeof(struct npe));
|
|
if (p_npe == NULL) {
|
|
printf("%s: Cannot allocate private hw data for eth_device %d",
|
|
__FUNCTION__, eth_num);
|
|
free(dev);
|
|
return -1;
|
|
}
|
|
memset(p_npe, 0, sizeof(struct npe));
|
|
|
|
switch (eth_num) {
|
|
default: /* fall through */
|
|
case 0:
|
|
memcpy(dev->enetaddr, bis->bi_enetaddr, 6);
|
|
p_npe->eth_id = 0;
|
|
p_npe->phy_no = CONFIG_PHY_ADDR;
|
|
break;
|
|
|
|
#ifdef CONFIG_HAS_ETH1
|
|
case 1:
|
|
memcpy(dev->enetaddr, bis->bi_enet1addr, 6);
|
|
p_npe->eth_id = 1;
|
|
p_npe->phy_no = CONFIG_PHY1_ADDR;
|
|
break;
|
|
#endif
|
|
}
|
|
|
|
sprintf(dev->name, "NPE%d", eth_num);
|
|
dev->priv = (void *)p_npe;
|
|
dev->init = npe_init;
|
|
dev->halt = npe_halt;
|
|
dev->send = npe_send;
|
|
dev->recv = npe_rx;
|
|
|
|
p_npe->print_speed = 1;
|
|
|
|
if (0 == virgin) {
|
|
virgin = 1;
|
|
|
|
if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X) {
|
|
switch (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK) {
|
|
case IX_FEATURE_CTRL_SILICON_TYPE_B0:
|
|
/*
|
|
* If it is B0 Silicon, we only enable port when its corresponding
|
|
* Eth Coprocessor is available.
|
|
*/
|
|
if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
|
|
IX_FEATURE_CTRL_COMPONENT_ENABLED)
|
|
npe_exists[IX_ETH_PORT_1] = TRUE;
|
|
|
|
if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
|
|
IX_FEATURE_CTRL_COMPONENT_ENABLED)
|
|
npe_exists[IX_ETH_PORT_2] = TRUE;
|
|
break;
|
|
case IX_FEATURE_CTRL_SILICON_TYPE_A0:
|
|
/*
|
|
* If it is A0 Silicon, we enable both as both Eth Coprocessors
|
|
* are available.
|
|
*/
|
|
npe_exists[IX_ETH_PORT_1] = TRUE;
|
|
npe_exists[IX_ETH_PORT_2] = TRUE;
|
|
break;
|
|
}
|
|
} else if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP46X) {
|
|
if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
|
|
IX_FEATURE_CTRL_COMPONENT_ENABLED)
|
|
npe_exists[IX_ETH_PORT_1] = TRUE;
|
|
|
|
if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
|
|
IX_FEATURE_CTRL_COMPONENT_ENABLED)
|
|
npe_exists[IX_ETH_PORT_2] = TRUE;
|
|
}
|
|
|
|
npe_used[IX_ETH_PORT_1] = 1;
|
|
npe_used[IX_ETH_PORT_2] = 1;
|
|
|
|
npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool);
|
|
npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool +
|
|
CFG_CACHELINE_SIZE - 1)
|
|
& ~(CFG_CACHELINE_SIZE - 1));
|
|
|
|
if (!npe_csr_load())
|
|
return 0;
|
|
}
|
|
|
|
eth_register(dev);
|
|
|
|
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
|
|
miiphy_register(dev->name, npe_miiphy_read, npe_miiphy_write);
|
|
#endif
|
|
|
|
} /* end for each supported device */
|
|
|
|
return 1;
|
|
}
|
|
|
|
#endif /* CONFIG_IXP4XX_NPE */
|