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![Robert P. J. Day](/assets/img/avatar_default.png)
Aesthetic cleanup in drivers/video/exynos_dp*.[ch] files. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
962 lines
24 KiB
C
962 lines
24 KiB
C
/*
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* Copyright (C) 2012 Samsung Electronics
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*
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* Author: Donghwa Lee <dh09.lee@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <malloc.h>
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#include <linux/compat.h>
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#include <linux/err.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/dp_info.h>
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#include <asm/arch/dp.h>
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#include <fdtdec.h>
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#include <libfdt.h>
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#include "exynos_dp_lowlevel.h"
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DECLARE_GLOBAL_DATA_PTR;
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void __exynos_set_dp_phy(unsigned int onoff)
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{
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}
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void exynos_set_dp_phy(unsigned int onoff)
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__attribute__((weak, alias("__exynos_set_dp_phy")));
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static void exynos_dp_disp_info(struct edp_disp_info *disp_info)
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{
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disp_info->h_total = disp_info->h_res + disp_info->h_sync_width +
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disp_info->h_back_porch + disp_info->h_front_porch;
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disp_info->v_total = disp_info->v_res + disp_info->v_sync_width +
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disp_info->v_back_porch + disp_info->v_front_porch;
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return;
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}
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static int exynos_dp_init_dp(void)
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{
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int ret;
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exynos_dp_reset();
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/* SW defined function Normal operation */
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exynos_dp_enable_sw_func(DP_ENABLE);
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ret = exynos_dp_init_analog_func();
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if (ret != EXYNOS_DP_SUCCESS)
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return ret;
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exynos_dp_init_hpd();
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exynos_dp_init_aux();
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return ret;
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}
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static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
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{
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int i;
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unsigned char sum = 0;
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for (i = 0; i < EDID_BLOCK_LENGTH; i++)
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sum = sum + edid_data[i];
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return sum;
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}
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static unsigned int exynos_dp_read_edid(void)
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{
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unsigned char edid[EDID_BLOCK_LENGTH * 2];
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unsigned int extend_block = 0;
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unsigned char sum;
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unsigned char test_vector;
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int retval;
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/*
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* EDID device address is 0x50.
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* However, if necessary, you must have set upper address
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* into E-EDID in I2C device, 0x30.
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*/
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/* Read Extension Flag, Number of 128-byte EDID extension blocks */
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exynos_dp_read_byte_from_i2c(I2C_EDID_DEVICE_ADDR, EDID_EXTENSION_FLAG,
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&extend_block);
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if (extend_block > 0) {
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printf("DP EDID data includes a single extension!\n");
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/* Read EDID data */
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retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
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EDID_HEADER_PATTERN,
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EDID_BLOCK_LENGTH,
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&edid[EDID_HEADER_PATTERN]);
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if (retval != 0) {
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printf("DP EDID Read failed!\n");
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return -1;
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}
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sum = exynos_dp_calc_edid_check_sum(edid);
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if (sum != 0) {
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printf("DP EDID bad checksum!\n");
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return -1;
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}
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/* Read additional EDID data */
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retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
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EDID_BLOCK_LENGTH,
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EDID_BLOCK_LENGTH,
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&edid[EDID_BLOCK_LENGTH]);
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if (retval != 0) {
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printf("DP EDID Read failed!\n");
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return -1;
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}
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sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
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if (sum != 0) {
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printf("DP EDID bad checksum!\n");
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return -1;
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}
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exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST,
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&test_vector);
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if (test_vector & DPCD_TEST_EDID_READ) {
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exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM,
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edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
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exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
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DPCD_TEST_EDID_CHECKSUM_WRITE);
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}
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} else {
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debug("DP EDID data does not include any extensions.\n");
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/* Read EDID data */
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retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
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EDID_HEADER_PATTERN,
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EDID_BLOCK_LENGTH,
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&edid[EDID_HEADER_PATTERN]);
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if (retval != 0) {
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printf("DP EDID Read failed!\n");
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return -1;
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}
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sum = exynos_dp_calc_edid_check_sum(edid);
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if (sum != 0) {
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printf("DP EDID bad checksum!\n");
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return -1;
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}
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exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST,
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&test_vector);
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if (test_vector & DPCD_TEST_EDID_READ) {
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exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM,
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edid[EDID_CHECKSUM]);
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exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
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DPCD_TEST_EDID_CHECKSUM_WRITE);
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}
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}
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debug("DP EDID Read success!\n");
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return 0;
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}
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static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
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{
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unsigned char buf[12];
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unsigned int ret;
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unsigned char temp;
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unsigned char retry_cnt;
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unsigned char dpcd_rev[16];
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unsigned char lane_bw[16];
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unsigned char lane_cnt[16];
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memset(dpcd_rev, 0, 16);
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memset(lane_bw, 0, 16);
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memset(lane_cnt, 0, 16);
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memset(buf, 0, 12);
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retry_cnt = 5;
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while (retry_cnt) {
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/* Read DPCD 0x0000-0x000b */
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ret = exynos_dp_read_bytes_from_dpcd(DPCD_DPCD_REV, 12,
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buf);
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if (ret != EXYNOS_DP_SUCCESS) {
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if (retry_cnt == 0) {
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printf("DP read_byte_from_dpcd() failed\n");
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return ret;
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}
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retry_cnt--;
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} else
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break;
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}
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/* */
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temp = buf[DPCD_DPCD_REV];
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if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11)
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edp_info->dpcd_rev = temp;
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else {
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printf("DP Wrong DPCD Rev : %x\n", temp);
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return -ENODEV;
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}
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temp = buf[DPCD_MAX_LINK_RATE];
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if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70)
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edp_info->lane_bw = temp;
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else {
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printf("DP Wrong MAX LINK RATE : %x\n", temp);
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return -EINVAL;
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}
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/* Refer VESA Display Port Standard Ver1.1a Page 120 */
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if (edp_info->dpcd_rev == DP_DPCD_REV_11) {
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temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f;
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if (buf[DPCD_MAX_LANE_COUNT] & 0x80)
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edp_info->dpcd_efc = 1;
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else
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edp_info->dpcd_efc = 0;
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} else {
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temp = buf[DPCD_MAX_LANE_COUNT];
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edp_info->dpcd_efc = 0;
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}
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if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 ||
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temp == DP_LANE_CNT_4) {
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edp_info->lane_cnt = temp;
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} else {
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printf("DP Wrong MAX LANE COUNT : %x\n", temp);
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return -EINVAL;
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}
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ret = exynos_dp_read_edid();
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if (ret != EXYNOS_DP_SUCCESS) {
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printf("DP exynos_dp_read_edid() failed\n");
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return -EINVAL;
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}
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return ret;
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}
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static void exynos_dp_init_training(void)
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{
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/*
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* MACRO_RST must be applied after the PLL_LOCK to avoid
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* the DP inter pair skew issue for at least 10 us
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*/
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exynos_dp_reset_macro();
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/* All DP analog module power up */
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exynos_dp_set_analog_power_down(POWER_ALL, 0);
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}
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static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info)
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{
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unsigned char buf[5];
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unsigned int ret = 0;
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debug("DP: %s was called\n", __func__);
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edp_info->lt_info.lt_status = DP_LT_CR;
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edp_info->lt_info.ep_loop = 0;
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edp_info->lt_info.cr_loop[0] = 0;
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edp_info->lt_info.cr_loop[1] = 0;
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edp_info->lt_info.cr_loop[2] = 0;
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edp_info->lt_info.cr_loop[3] = 0;
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/* Set sink to D0 (Sink Not Ready) mode. */
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ret = exynos_dp_write_byte_to_dpcd(DPCD_SINK_POWER_STATE,
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DPCD_SET_POWER_STATE_D0);
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if (ret != EXYNOS_DP_SUCCESS) {
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printf("DP write_dpcd_byte failed\n");
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return ret;
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}
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/* Set link rate and count as you want to establish */
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exynos_dp_set_link_bandwidth(edp_info->lane_bw);
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exynos_dp_set_lane_count(edp_info->lane_cnt);
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/* Setup RX configuration */
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buf[0] = edp_info->lane_bw;
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buf[1] = edp_info->lane_cnt;
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ret = exynos_dp_write_bytes_to_dpcd(DPCD_LINK_BW_SET, 2,
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buf);
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if (ret != EXYNOS_DP_SUCCESS) {
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printf("DP write_dpcd_byte failed\n");
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return ret;
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}
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exynos_dp_set_lane_pre_emphasis(PRE_EMPHASIS_LEVEL_0,
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edp_info->lane_cnt);
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/* Set training pattern 1 */
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exynos_dp_set_training_pattern(TRAINING_PTN1);
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/* Set RX training pattern */
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buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1;
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buf[1] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
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DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
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buf[2] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
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DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
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buf[3] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
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DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
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buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
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DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
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ret = exynos_dp_write_bytes_to_dpcd(DPCD_TRAINING_PATTERN_SET,
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5, buf);
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if (ret != EXYNOS_DP_SUCCESS) {
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printf("DP write_dpcd_byte failed\n");
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return ret;
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}
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return ret;
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}
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static unsigned int exynos_dp_training_pattern_dis(void)
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{
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unsigned int ret = EXYNOS_DP_SUCCESS;
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exynos_dp_set_training_pattern(DP_NONE);
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ret = exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
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DPCD_TRAINING_PATTERN_DISABLED);
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if (ret != EXYNOS_DP_SUCCESS) {
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printf("DP request_link_training_req failed\n");
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return -EAGAIN;
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}
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return ret;
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}
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static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable)
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{
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unsigned char data;
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unsigned int ret = EXYNOS_DP_SUCCESS;
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ret = exynos_dp_read_byte_from_dpcd(DPCD_LANE_COUNT_SET,
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&data);
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if (ret != EXYNOS_DP_SUCCESS) {
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printf("DP read_from_dpcd failed\n");
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return -EAGAIN;
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}
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if (enable)
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data = DPCD_ENHANCED_FRAME_EN | DPCD_LN_COUNT_SET(data);
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else
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data = DPCD_LN_COUNT_SET(data);
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ret = exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET,
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data);
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if (ret != EXYNOS_DP_SUCCESS) {
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printf("DP write_to_dpcd failed\n");
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return -EAGAIN;
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}
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return ret;
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}
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static unsigned int exynos_dp_set_enhanced_mode(unsigned char enhance_mode)
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{
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unsigned int ret = EXYNOS_DP_SUCCESS;
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ret = exynos_dp_enable_rx_to_enhanced_mode(enhance_mode);
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if (ret != EXYNOS_DP_SUCCESS) {
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printf("DP rx_enhance_mode failed\n");
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return -EAGAIN;
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}
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exynos_dp_enable_enhanced_mode(enhance_mode);
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return ret;
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}
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static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info *edp_info,
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unsigned char *status)
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{
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unsigned int ret, i;
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unsigned char buf[2];
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unsigned char lane_stat[DP_LANE_CNT_4] = {0,};
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unsigned char shift_val[DP_LANE_CNT_4] = {0,};
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shift_val[0] = 0;
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shift_val[1] = 4;
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shift_val[2] = 0;
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shift_val[3] = 4;
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ret = exynos_dp_read_bytes_from_dpcd(DPCD_LANE0_1_STATUS, 2, buf);
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if (ret != EXYNOS_DP_SUCCESS) {
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printf("DP read lane status failed\n");
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return ret;
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}
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for (i = 0; i < edp_info->lane_cnt; i++) {
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lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f;
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if (lane_stat[0] != lane_stat[i]) {
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printf("Wrong lane status\n");
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return -EINVAL;
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}
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}
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*status = lane_stat[0];
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return ret;
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}
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static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num,
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unsigned char *sw, unsigned char *em)
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{
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unsigned int ret = EXYNOS_DP_SUCCESS;
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unsigned char buf;
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unsigned int dpcd_addr;
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unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
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/* lane_num value is used as array index, so this range 0 ~ 3 */
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dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
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ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf);
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if (ret != EXYNOS_DP_SUCCESS) {
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printf("DP read adjust request failed\n");
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return -EAGAIN;
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}
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*sw = ((buf >> shift_val[lane_num]) & 0x03);
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*em = ((buf >> shift_val[lane_num]) & 0x0c) >> 2;
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return ret;
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}
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static int exynos_dp_equalizer_err_link(struct edp_device_info *edp_info)
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{
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int ret;
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ret = exynos_dp_training_pattern_dis();
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if (ret != EXYNOS_DP_SUCCESS) {
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printf("DP training_pattern_disable() failed\n");
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edp_info->lt_info.lt_status = DP_LT_FAIL;
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}
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ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc);
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if (ret != EXYNOS_DP_SUCCESS) {
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printf("DP set_enhanced_mode() failed\n");
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edp_info->lt_info.lt_status = DP_LT_FAIL;
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}
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return ret;
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}
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static int exynos_dp_reduce_link_rate(struct edp_device_info *edp_info)
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{
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int ret;
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if (edp_info->lane_bw == DP_LANE_BW_2_70) {
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edp_info->lane_bw = DP_LANE_BW_1_62;
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printf("DP Change lane bw to 1.62Gbps\n");
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edp_info->lt_info.lt_status = DP_LT_START;
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ret = EXYNOS_DP_SUCCESS;
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} else {
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ret = exynos_dp_training_pattern_dis();
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if (ret != EXYNOS_DP_SUCCESS)
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printf("DP training_patter_disable() failed\n");
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ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc);
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if (ret != EXYNOS_DP_SUCCESS)
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printf("DP set_enhanced_mode() failed\n");
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edp_info->lt_info.lt_status = DP_LT_FAIL;
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}
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return ret;
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}
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static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
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*edp_info)
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{
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unsigned int ret = EXYNOS_DP_SUCCESS;
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unsigned char lane_stat;
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unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, };
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unsigned int i;
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unsigned char adj_req_sw;
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unsigned char adj_req_em;
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unsigned char buf[5];
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debug("DP: %s was called\n", __func__);
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mdelay(1);
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ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
|
|
if (ret != EXYNOS_DP_SUCCESS) {
|
|
printf("DP read lane status failed\n");
|
|
edp_info->lt_info.lt_status = DP_LT_FAIL;
|
|
return ret;
|
|
}
|
|
|
|
if (lane_stat & DP_LANE_STAT_CR_DONE) {
|
|
debug("DP clock Recovery training succeed\n");
|
|
exynos_dp_set_training_pattern(TRAINING_PTN2);
|
|
|
|
for (i = 0; i < edp_info->lane_cnt; i++) {
|
|
ret = exynos_dp_read_dpcd_adj_req(i, &adj_req_sw,
|
|
&adj_req_em);
|
|
if (ret != EXYNOS_DP_SUCCESS) {
|
|
edp_info->lt_info.lt_status = DP_LT_FAIL;
|
|
return ret;
|
|
}
|
|
|
|
lt_ctl_val[i] = 0;
|
|
lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
|
|
|
|
if ((adj_req_sw == VOLTAGE_LEVEL_3)
|
|
|| (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
|
|
lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
|
|
MAX_PRE_EMPHASIS_REACH_3;
|
|
}
|
|
exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i);
|
|
}
|
|
|
|
buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2;
|
|
buf[1] = lt_ctl_val[0];
|
|
buf[2] = lt_ctl_val[1];
|
|
buf[3] = lt_ctl_val[2];
|
|
buf[4] = lt_ctl_val[3];
|
|
|
|
ret = exynos_dp_write_bytes_to_dpcd(
|
|
DPCD_TRAINING_PATTERN_SET, 5, buf);
|
|
if (ret != EXYNOS_DP_SUCCESS) {
|
|
printf("DP write training pattern1 failed\n");
|
|
edp_info->lt_info.lt_status = DP_LT_FAIL;
|
|
return ret;
|
|
} else
|
|
edp_info->lt_info.lt_status = DP_LT_ET;
|
|
} else {
|
|
for (i = 0; i < edp_info->lane_cnt; i++) {
|
|
lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(i);
|
|
ret = exynos_dp_read_dpcd_adj_req(i,
|
|
&adj_req_sw, &adj_req_em);
|
|
if (ret != EXYNOS_DP_SUCCESS) {
|
|
printf("DP read adj req failed\n");
|
|
edp_info->lt_info.lt_status = DP_LT_FAIL;
|
|
return ret;
|
|
}
|
|
|
|
if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
|
|
(adj_req_em == PRE_EMPHASIS_LEVEL_3))
|
|
ret = exynos_dp_reduce_link_rate(edp_info);
|
|
|
|
if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) ==
|
|
adj_req_sw) &&
|
|
(PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) ==
|
|
adj_req_em)) {
|
|
edp_info->lt_info.cr_loop[i]++;
|
|
if (edp_info->lt_info.cr_loop[i] == MAX_CR_LOOP)
|
|
ret = exynos_dp_reduce_link_rate(
|
|
edp_info);
|
|
}
|
|
|
|
lt_ctl_val[i] = 0;
|
|
lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
|
|
|
|
if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
|
|
(adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
|
|
lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
|
|
MAX_PRE_EMPHASIS_REACH_3;
|
|
}
|
|
exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i);
|
|
}
|
|
|
|
ret = exynos_dp_write_bytes_to_dpcd(
|
|
DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val);
|
|
if (ret != EXYNOS_DP_SUCCESS) {
|
|
printf("DP write training pattern2 failed\n");
|
|
edp_info->lt_info.lt_status = DP_LT_FAIL;
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
|
|
*edp_info)
|
|
{
|
|
unsigned int ret = EXYNOS_DP_SUCCESS;
|
|
unsigned char lane_stat, adj_req_sw, adj_req_em, i;
|
|
unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,};
|
|
unsigned char interlane_aligned = 0;
|
|
unsigned char f_bw;
|
|
unsigned char f_lane_cnt;
|
|
unsigned char sink_stat;
|
|
|
|
mdelay(1);
|
|
|
|
ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
|
|
if (ret != EXYNOS_DP_SUCCESS) {
|
|
printf("DP read lane status failed\n");
|
|
edp_info->lt_info.lt_status = DP_LT_FAIL;
|
|
return ret;
|
|
}
|
|
|
|
debug("DP lane stat : %x\n", lane_stat);
|
|
|
|
if (lane_stat & DP_LANE_STAT_CR_DONE) {
|
|
ret = exynos_dp_read_byte_from_dpcd(DPCD_LN_ALIGN_UPDATED,
|
|
&sink_stat);
|
|
if (ret != EXYNOS_DP_SUCCESS) {
|
|
edp_info->lt_info.lt_status = DP_LT_FAIL;
|
|
|
|
return ret;
|
|
}
|
|
|
|
interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE);
|
|
|
|
for (i = 0; i < edp_info->lane_cnt; i++) {
|
|
ret = exynos_dp_read_dpcd_adj_req(i,
|
|
&adj_req_sw, &adj_req_em);
|
|
if (ret != EXYNOS_DP_SUCCESS) {
|
|
printf("DP read adj req 1 failed\n");
|
|
edp_info->lt_info.lt_status = DP_LT_FAIL;
|
|
|
|
return ret;
|
|
}
|
|
|
|
lt_ctl_val[i] = 0;
|
|
lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
|
|
|
|
if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
|
|
(adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
|
|
lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3;
|
|
lt_ctl_val[i] |= MAX_PRE_EMPHASIS_REACH_3;
|
|
}
|
|
}
|
|
|
|
if (((lane_stat&DP_LANE_STAT_CE_DONE) &&
|
|
(lane_stat&DP_LANE_STAT_SYM_LOCK))
|
|
&& (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) {
|
|
debug("DP Equalizer training succeed\n");
|
|
|
|
f_bw = exynos_dp_get_link_bandwidth();
|
|
f_lane_cnt = exynos_dp_get_lane_count();
|
|
|
|
debug("DP final BandWidth : %x\n", f_bw);
|
|
debug("DP final Lane Count : %x\n", f_lane_cnt);
|
|
|
|
edp_info->lt_info.lt_status = DP_LT_FINISHED;
|
|
|
|
exynos_dp_equalizer_err_link(edp_info);
|
|
|
|
} else {
|
|
edp_info->lt_info.ep_loop++;
|
|
|
|
if (edp_info->lt_info.ep_loop > MAX_EQ_LOOP) {
|
|
if (edp_info->lane_bw == DP_LANE_BW_2_70) {
|
|
ret = exynos_dp_reduce_link_rate(
|
|
edp_info);
|
|
} else {
|
|
edp_info->lt_info.lt_status =
|
|
DP_LT_FAIL;
|
|
exynos_dp_equalizer_err_link(edp_info);
|
|
}
|
|
} else {
|
|
for (i = 0; i < edp_info->lane_cnt; i++)
|
|
exynos_dp_set_lanex_pre_emphasis(
|
|
lt_ctl_val[i], i);
|
|
|
|
ret = exynos_dp_write_bytes_to_dpcd(
|
|
DPCD_TRAINING_LANE0_SET,
|
|
4, lt_ctl_val);
|
|
if (ret != EXYNOS_DP_SUCCESS) {
|
|
printf("DP set lt pattern failed\n");
|
|
edp_info->lt_info.lt_status =
|
|
DP_LT_FAIL;
|
|
exynos_dp_equalizer_err_link(edp_info);
|
|
}
|
|
}
|
|
}
|
|
} else if (edp_info->lane_bw == DP_LANE_BW_2_70) {
|
|
ret = exynos_dp_reduce_link_rate(edp_info);
|
|
} else {
|
|
edp_info->lt_info.lt_status = DP_LT_FAIL;
|
|
exynos_dp_equalizer_err_link(edp_info);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static unsigned int exynos_dp_sw_link_training(struct edp_device_info *edp_info)
|
|
{
|
|
unsigned int ret = 0;
|
|
int training_finished;
|
|
|
|
/* Turn off unnecessary lane */
|
|
if (edp_info->lane_cnt == 1)
|
|
exynos_dp_set_analog_power_down(CH1_BLOCK, 1);
|
|
|
|
training_finished = 0;
|
|
|
|
edp_info->lt_info.lt_status = DP_LT_START;
|
|
|
|
/* Process here */
|
|
while (!training_finished) {
|
|
switch (edp_info->lt_info.lt_status) {
|
|
case DP_LT_START:
|
|
ret = exynos_dp_link_start(edp_info);
|
|
if (ret != EXYNOS_DP_SUCCESS) {
|
|
printf("DP LT:link start failed\n");
|
|
return ret;
|
|
}
|
|
break;
|
|
case DP_LT_CR:
|
|
ret = exynos_dp_process_clock_recovery(edp_info);
|
|
if (ret != EXYNOS_DP_SUCCESS) {
|
|
printf("DP LT:clock recovery failed\n");
|
|
return ret;
|
|
}
|
|
break;
|
|
case DP_LT_ET:
|
|
ret = exynos_dp_process_equalizer_training(edp_info);
|
|
if (ret != EXYNOS_DP_SUCCESS) {
|
|
printf("DP LT:equalizer training failed\n");
|
|
return ret;
|
|
}
|
|
break;
|
|
case DP_LT_FINISHED:
|
|
training_finished = 1;
|
|
break;
|
|
case DP_LT_FAIL:
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static unsigned int exynos_dp_set_link_train(struct edp_device_info *edp_info)
|
|
{
|
|
unsigned int ret;
|
|
|
|
exynos_dp_init_training();
|
|
|
|
ret = exynos_dp_sw_link_training(edp_info);
|
|
if (ret != EXYNOS_DP_SUCCESS)
|
|
printf("DP dp_sw_link_training() failed\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void exynos_dp_enable_scramble(unsigned int enable)
|
|
{
|
|
unsigned char data;
|
|
|
|
if (enable) {
|
|
exynos_dp_enable_scrambling(DP_ENABLE);
|
|
|
|
exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET,
|
|
&data);
|
|
exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
|
|
(u8)(data & ~DPCD_SCRAMBLING_DISABLED));
|
|
} else {
|
|
exynos_dp_enable_scrambling(DP_DISABLE);
|
|
exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET,
|
|
&data);
|
|
exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
|
|
(u8)(data | DPCD_SCRAMBLING_DISABLED));
|
|
}
|
|
}
|
|
|
|
static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info)
|
|
{
|
|
unsigned int ret = 0;
|
|
unsigned int retry_cnt;
|
|
|
|
mdelay(1);
|
|
|
|
if (edp_info->video_info.master_mode) {
|
|
printf("DP does not support master mode\n");
|
|
return -ENODEV;
|
|
} else {
|
|
/* debug slave */
|
|
exynos_dp_config_video_slave_mode(&edp_info->video_info);
|
|
}
|
|
|
|
exynos_dp_set_video_color_format(&edp_info->video_info);
|
|
|
|
if (edp_info->video_info.bist_mode) {
|
|
if (exynos_dp_config_video_bist(edp_info) != 0)
|
|
return -1;
|
|
}
|
|
|
|
ret = exynos_dp_get_pll_lock_status();
|
|
if (ret != PLL_LOCKED) {
|
|
printf("DP PLL is not locked yet\n");
|
|
return -EIO;
|
|
}
|
|
|
|
if (edp_info->video_info.master_mode == 0) {
|
|
retry_cnt = 10;
|
|
while (retry_cnt) {
|
|
ret = exynos_dp_is_slave_video_stream_clock_on();
|
|
if (ret != EXYNOS_DP_SUCCESS) {
|
|
if (retry_cnt == 0) {
|
|
printf("DP stream_clock_on failed\n");
|
|
return ret;
|
|
}
|
|
retry_cnt--;
|
|
mdelay(1);
|
|
} else
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Set to use the register calculated M/N video */
|
|
exynos_dp_set_video_cr_mn(CALCULATED_M, 0, 0);
|
|
|
|
/* For video bist, Video timing must be generated by register */
|
|
exynos_dp_set_video_timing_mode(VIDEO_TIMING_FROM_CAPTURE);
|
|
|
|
/* Enable video bist */
|
|
if (edp_info->video_info.bist_pattern != COLOR_RAMP &&
|
|
edp_info->video_info.bist_pattern != BALCK_WHITE_V_LINES &&
|
|
edp_info->video_info.bist_pattern != COLOR_SQUARE)
|
|
exynos_dp_enable_video_bist(edp_info->video_info.bist_mode);
|
|
else
|
|
exynos_dp_enable_video_bist(DP_DISABLE);
|
|
|
|
/* Disable video mute */
|
|
exynos_dp_enable_video_mute(DP_DISABLE);
|
|
|
|
/* Configure video Master or Slave mode */
|
|
exynos_dp_enable_video_master(edp_info->video_info.master_mode);
|
|
|
|
/* Enable video */
|
|
exynos_dp_start_video();
|
|
|
|
if (edp_info->video_info.master_mode == 0) {
|
|
retry_cnt = 100;
|
|
while (retry_cnt) {
|
|
ret = exynos_dp_is_video_stream_on();
|
|
if (ret != EXYNOS_DP_SUCCESS) {
|
|
if (retry_cnt == 0) {
|
|
printf("DP Timeout of video stream\n");
|
|
return ret;
|
|
}
|
|
retry_cnt--;
|
|
mdelay(5);
|
|
} else
|
|
break;
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int exynos_dp_parse_dt(const void *blob, struct edp_device_info *edp_info)
|
|
{
|
|
unsigned int node = fdtdec_next_compatible(blob, 0,
|
|
COMPAT_SAMSUNG_EXYNOS5_DP);
|
|
if (node <= 0) {
|
|
debug("exynos_dp: Can't get device node for dp\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
edp_info->disp_info.h_res = fdtdec_get_int(blob, node,
|
|
"samsung,h-res", 0);
|
|
edp_info->disp_info.h_sync_width = fdtdec_get_int(blob, node,
|
|
"samsung,h-sync-width", 0);
|
|
edp_info->disp_info.h_back_porch = fdtdec_get_int(blob, node,
|
|
"samsung,h-back-porch", 0);
|
|
edp_info->disp_info.h_front_porch = fdtdec_get_int(blob, node,
|
|
"samsung,h-front-porch", 0);
|
|
edp_info->disp_info.v_res = fdtdec_get_int(blob, node,
|
|
"samsung,v-res", 0);
|
|
edp_info->disp_info.v_sync_width = fdtdec_get_int(blob, node,
|
|
"samsung,v-sync-width", 0);
|
|
edp_info->disp_info.v_back_porch = fdtdec_get_int(blob, node,
|
|
"samsung,v-back-porch", 0);
|
|
edp_info->disp_info.v_front_porch = fdtdec_get_int(blob, node,
|
|
"samsung,v-front-porch", 0);
|
|
edp_info->disp_info.v_sync_rate = fdtdec_get_int(blob, node,
|
|
"samsung,v-sync-rate", 0);
|
|
|
|
edp_info->lt_info.lt_status = fdtdec_get_int(blob, node,
|
|
"samsung,lt-status", 0);
|
|
|
|
edp_info->video_info.master_mode = fdtdec_get_int(blob, node,
|
|
"samsung,master-mode", 0);
|
|
edp_info->video_info.bist_mode = fdtdec_get_int(blob, node,
|
|
"samsung,bist-mode", 0);
|
|
edp_info->video_info.bist_pattern = fdtdec_get_int(blob, node,
|
|
"samsung,bist-pattern", 0);
|
|
edp_info->video_info.h_sync_polarity = fdtdec_get_int(blob, node,
|
|
"samsung,h-sync-polarity", 0);
|
|
edp_info->video_info.v_sync_polarity = fdtdec_get_int(blob, node,
|
|
"samsung,v-sync-polarity", 0);
|
|
edp_info->video_info.interlaced = fdtdec_get_int(blob, node,
|
|
"samsung,interlaced", 0);
|
|
edp_info->video_info.color_space = fdtdec_get_int(blob, node,
|
|
"samsung,color-space", 0);
|
|
edp_info->video_info.dynamic_range = fdtdec_get_int(blob, node,
|
|
"samsung,dynamic-range", 0);
|
|
edp_info->video_info.ycbcr_coeff = fdtdec_get_int(blob, node,
|
|
"samsung,ycbcr-coeff", 0);
|
|
edp_info->video_info.color_depth = fdtdec_get_int(blob, node,
|
|
"samsung,color-depth", 0);
|
|
return 0;
|
|
}
|
|
|
|
unsigned int exynos_init_dp(void)
|
|
{
|
|
unsigned int ret;
|
|
struct edp_device_info *edp_info;
|
|
|
|
edp_info = kzalloc(sizeof(struct edp_device_info), GFP_KERNEL);
|
|
if (!edp_info) {
|
|
debug("failed to allocate edp device object.\n");
|
|
return -EFAULT;
|
|
}
|
|
|
|
if (exynos_dp_parse_dt(gd->fdt_blob, edp_info))
|
|
debug("unable to parse DP DT node\n");
|
|
|
|
exynos_dp_set_base_addr();
|
|
|
|
exynos_dp_disp_info(&edp_info->disp_info);
|
|
|
|
exynos_set_dp_phy(1);
|
|
|
|
ret = exynos_dp_init_dp();
|
|
if (ret != EXYNOS_DP_SUCCESS) {
|
|
printf("DP exynos_dp_init_dp() failed\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = exynos_dp_handle_edid(edp_info);
|
|
if (ret != EXYNOS_DP_SUCCESS) {
|
|
printf("EDP handle_edid fail\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = exynos_dp_set_link_train(edp_info);
|
|
if (ret != EXYNOS_DP_SUCCESS) {
|
|
printf("DP link training fail\n");
|
|
return ret;
|
|
}
|
|
|
|
exynos_dp_enable_scramble(DP_ENABLE);
|
|
exynos_dp_enable_rx_to_enhanced_mode(DP_ENABLE);
|
|
exynos_dp_enable_enhanced_mode(DP_ENABLE);
|
|
|
|
exynos_dp_set_link_bandwidth(edp_info->lane_bw);
|
|
exynos_dp_set_lane_count(edp_info->lane_cnt);
|
|
|
|
exynos_dp_init_video();
|
|
ret = exynos_dp_config_video(edp_info);
|
|
if (ret != EXYNOS_DP_SUCCESS) {
|
|
printf("Exynos DP init failed\n");
|
|
return ret;
|
|
}
|
|
|
|
debug("Exynos DP init done\n");
|
|
|
|
return ret;
|
|
}
|