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![Marek Vasut](/assets/img/avatar_default.png)
Add 32bpp framebuffer support for the Atmel HLCDC driver. This is needed for output bpp higher than 16bpp. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
221 lines
6.0 KiB
C
221 lines
6.0 KiB
C
/*
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* Driver for AT91/AT32 MULTI LAYER LCD Controller
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*
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* Copyright (C) 2012 Atmel Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/clk.h>
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#include <lcd.h>
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#include <atmel_hlcdc.h>
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#if defined(CONFIG_LCD_LOGO)
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#include <bmp_logo.h>
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#endif
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/* configurable parameters */
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#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
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#define ATMEL_LCDC_DMA_BURST_LEN 8
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#ifndef ATMEL_LCDC_GUARD_TIME
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#define ATMEL_LCDC_GUARD_TIME 1
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#endif
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#define ATMEL_LCDC_FIFO_SIZE 512
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#define lcdc_readl(reg) __raw_readl((reg))
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#define lcdc_writel(reg, val) __raw_writel((val), (reg))
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/*
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* the CLUT register map as following
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* RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0)
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*/
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void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
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{
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lcdc_writel(((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk)
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| ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk)
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| ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk),
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panel_info.mmio + ATMEL_LCDC_LUT(regno));
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}
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ushort *configuration_get_cmap(void)
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{
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#if defined(CONFIG_LCD_LOGO)
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return bmp_logo_palette;
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#else
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return NULL;
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#endif
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}
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void lcd_ctrl_init(void *lcdbase)
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{
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unsigned long value;
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struct lcd_dma_desc *desc;
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struct atmel_hlcd_regs *regs;
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if (!has_lcdc())
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return; /* No lcdc */
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regs = (struct atmel_hlcd_regs *)panel_info.mmio;
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/* Disable DISP signal */
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lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_DISPDIS);
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while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS))
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udelay(1);
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/* Disable synchronization */
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lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_SYNCDIS);
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while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS))
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udelay(1);
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/* Disable pixel clock */
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lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_CLKDIS);
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while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS))
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udelay(1);
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/* Disable PWM */
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lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_PWMDIS);
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while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
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udelay(1);
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/* Set pixel clock */
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value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
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if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
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value++;
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if (value < 1) {
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/* Using system clock as pixel clock */
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lcdc_writel(®s->lcdc_lcdcfg0,
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LCDC_LCDCFG0_CLKDIV(0)
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| LCDC_LCDCFG0_CGDISHCR
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| LCDC_LCDCFG0_CGDISHEO
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| LCDC_LCDCFG0_CGDISOVR1
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| LCDC_LCDCFG0_CGDISBASE
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| panel_info.vl_clk_pol
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| LCDC_LCDCFG0_CLKSEL);
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} else {
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lcdc_writel(®s->lcdc_lcdcfg0,
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LCDC_LCDCFG0_CLKDIV(value - 2)
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| LCDC_LCDCFG0_CGDISHCR
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| LCDC_LCDCFG0_CGDISHEO
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| LCDC_LCDCFG0_CGDISOVR1
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| LCDC_LCDCFG0_CGDISBASE
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| panel_info.vl_clk_pol);
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}
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/* Initialize control register 5 */
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value = 0;
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value |= panel_info.vl_sync;
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#ifndef LCD_OUTPUT_BPP
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/* Output is 24bpp */
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value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
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#else
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switch (LCD_OUTPUT_BPP) {
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case 12:
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value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
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break;
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case 16:
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value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
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break;
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case 18:
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value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
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break;
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case 24:
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value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
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break;
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default:
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BUG();
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break;
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}
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#endif
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value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME);
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value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
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lcdc_writel(®s->lcdc_lcdcfg5, value);
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/* Vertical & Horizontal Timing */
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value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1);
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value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
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lcdc_writel(®s->lcdc_lcdcfg1, value);
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value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin);
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value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1);
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lcdc_writel(®s->lcdc_lcdcfg2, value);
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value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1);
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value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1);
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lcdc_writel(®s->lcdc_lcdcfg3, value);
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/* Display size */
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value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1);
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value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1);
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lcdc_writel(®s->lcdc_lcdcfg4, value);
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lcdc_writel(®s->lcdc_basecfg0,
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LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO);
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switch (NBITS(panel_info.vl_bpix)) {
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case 16:
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lcdc_writel(®s->lcdc_basecfg1,
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LCDC_BASECFG1_RGBMODE_16BPP_RGB_565);
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break;
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case 32:
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lcdc_writel(®s->lcdc_basecfg1,
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LCDC_BASECFG1_RGBMODE_24BPP_RGB_888);
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break;
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default:
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BUG();
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break;
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}
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lcdc_writel(®s->lcdc_basecfg2, LCDC_BASECFG2_XSTRIDE(0));
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lcdc_writel(®s->lcdc_basecfg3, 0);
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lcdc_writel(®s->lcdc_basecfg4, LCDC_BASECFG4_DMA);
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/* Disable all interrupts */
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lcdc_writel(®s->lcdc_lcdidr, ~0UL);
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lcdc_writel(®s->lcdc_baseidr, ~0UL);
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/* Setup the DMA descriptor, this descriptor will loop to itself */
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desc = (struct lcd_dma_desc *)(lcdbase - 16);
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desc->address = (u32)lcdbase;
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/* Disable DMA transfer interrupt & descriptor loaded interrupt. */
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desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
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| LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
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desc->next = (u32)desc;
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/* Flush the DMA descriptor if we enabled dcache */
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flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
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lcdc_writel(®s->lcdc_baseaddr, desc->address);
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lcdc_writel(®s->lcdc_basectrl, desc->control);
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lcdc_writel(®s->lcdc_basenext, desc->next);
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lcdc_writel(®s->lcdc_basecher, LCDC_BASECHER_CHEN |
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LCDC_BASECHER_UPDATEEN);
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/* Enable LCD */
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value = lcdc_readl(®s->lcdc_lcden);
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lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_CLKEN);
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while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS))
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udelay(1);
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value = lcdc_readl(®s->lcdc_lcden);
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lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_SYNCEN);
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while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS))
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udelay(1);
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value = lcdc_readl(®s->lcdc_lcden);
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lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_DISPEN);
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while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS))
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udelay(1);
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value = lcdc_readl(®s->lcdc_lcden);
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lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_PWMEN);
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while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
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udelay(1);
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/* Enable flushing if we enabled dcache */
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lcd_set_flush_dcache(1);
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}
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