mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-21 18:39:43 +09:00
f2b85ab5e6
At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API. In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device. Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected. This patch includes Bin's fix-up patch from here: https://patchwork.ozlabs.org/patch/569478/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
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| .. | ||
| baytrail | ||
| coreboot | ||
| efi | ||
| ivybridge | ||
| qemu | ||
| quark | ||
| queensbay | ||
| call32.S | ||
| call64.S | ||
| config.mk | ||
| cpu_x86.c | ||
| cpu.c | ||
| interrupts.c | ||
| ioapic.c | ||
| irq.c | ||
| lapic.c | ||
| Makefile | ||
| mp_init.c | ||
| mtrr.c | ||
| pci.c | ||
| resetvec.S | ||
| sipi_vector.S | ||
| start16.S | ||
| start.S | ||
| turbo.c | ||
| u-boot.lds | ||