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https://github.com/brain-hackers/u-boot-brain
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![Bin Meng](/assets/img/avatar_default.png)
If pirq_routing_table points to NULL, that means U-Boot fails to generate the table before in create_pirq_routing_table(), so we test it against NULL before actually writing it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
217 lines
5.0 KiB
C
217 lines
5.0 KiB
C
/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/pci.h>
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#include <asm/pirq_routing.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct irq_router irq_router;
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static struct irq_routing_table *pirq_routing_table;
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bool pirq_check_irq_routed(int link, u8 irq)
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{
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u8 pirq;
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int base = irq_router.link_base;
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if (irq_router.config == PIRQ_VIA_PCI)
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pirq = x86_pci_read_config8(irq_router.bdf,
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LINK_N2V(link, base));
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else
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pirq = readb(irq_router.ibase + LINK_N2V(link, base));
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pirq &= 0xf;
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/* IRQ# 0/1/2/8/13 are reserved */
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if (pirq < 3 || pirq == 8 || pirq == 13)
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return false;
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return pirq == irq ? true : false;
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}
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int pirq_translate_link(int link)
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{
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return LINK_V2N(link, irq_router.link_base);
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}
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void pirq_assign_irq(int link, u8 irq)
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{
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int base = irq_router.link_base;
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/* IRQ# 0/1/2/8/13 are reserved */
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if (irq < 3 || irq == 8 || irq == 13)
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return;
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if (irq_router.config == PIRQ_VIA_PCI)
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x86_pci_write_config8(irq_router.bdf,
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LINK_N2V(link, base), irq);
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else
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writeb(irq, irq_router.ibase + LINK_N2V(link, base));
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}
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static inline void fill_irq_info(struct irq_info **slotp, int *entries, u8 bus,
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u8 device, u8 func, u8 pin, u8 pirq)
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{
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struct irq_info *slot = *slotp;
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slot->bus = bus;
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slot->devfn = (device << 3) | func;
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slot->irq[pin - 1].link = LINK_N2V(pirq, irq_router.link_base);
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slot->irq[pin - 1].bitmap = irq_router.irq_mask;
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(*entries)++;
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(*slotp)++;
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}
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__weak void cpu_irq_init(void)
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{
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return;
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}
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static int create_pirq_routing_table(void)
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{
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const void *blob = gd->fdt_blob;
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struct fdt_pci_addr addr;
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int node;
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int len, count;
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const u32 *cell;
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struct irq_routing_table *rt;
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struct irq_info *slot;
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int irq_entries = 0;
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int i;
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int ret;
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node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_IRQ_ROUTER);
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if (node < 0) {
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debug("%s: Cannot find irq router node\n", __func__);
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return -EINVAL;
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}
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ret = fdtdec_get_pci_addr(blob, node, FDT_PCI_SPACE_CONFIG,
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"reg", &addr);
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if (ret)
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return ret;
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/* extract the bdf from fdt_pci_addr */
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irq_router.bdf = addr.phys_hi & 0xffff00;
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ret = fdt_find_string(blob, node, "intel,pirq-config", "pci");
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if (!ret) {
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irq_router.config = PIRQ_VIA_PCI;
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} else {
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ret = fdt_find_string(blob, node, "intel,pirq-config", "ibase");
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if (!ret)
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irq_router.config = PIRQ_VIA_IBASE;
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else
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return -EINVAL;
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}
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ret = fdtdec_get_int_array(blob, node, "intel,pirq-link",
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&irq_router.link_base, 1);
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if (ret)
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return ret;
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irq_router.irq_mask = fdtdec_get_int(blob, node,
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"intel,pirq-mask", PIRQ_BITMAP);
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if (irq_router.config == PIRQ_VIA_IBASE) {
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int ibase_off;
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ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0);
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if (!ibase_off)
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return -EINVAL;
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/*
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* Here we assume that the IBASE register has already been
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* properly configured by U-Boot before.
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*
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* By 'valid' we mean:
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* 1) a valid memory space carved within system memory space
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* assigned to IBASE register block.
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* 2) memory range decoding is enabled.
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* Hence we don't do any santify test here.
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*/
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irq_router.ibase = x86_pci_read_config32(irq_router.bdf,
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ibase_off);
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irq_router.ibase &= ~0xf;
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}
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cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
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if (!cell)
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return -EINVAL;
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if ((len % sizeof(struct pirq_routing)) == 0)
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count = len / sizeof(struct pirq_routing);
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else
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return -EINVAL;
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rt = malloc(sizeof(struct irq_routing_table));
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if (!rt)
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return -ENOMEM;
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memset((char *)rt, 0, sizeof(struct irq_routing_table));
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/* Populate the PIRQ table fields */
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rt->signature = PIRQ_SIGNATURE;
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rt->version = PIRQ_VERSION;
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rt->rtr_bus = 0;
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rt->rtr_devfn = (PCI_DEV(irq_router.bdf) << 3) |
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PCI_FUNC(irq_router.bdf);
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rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
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rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
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slot = rt->slots;
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/* Now fill in the irq_info entries in the PIRQ table */
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for (i = 0; i < count; i++) {
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struct pirq_routing pr;
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pr.bdf = fdt_addr_to_cpu(cell[0]);
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pr.pin = fdt_addr_to_cpu(cell[1]);
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pr.pirq = fdt_addr_to_cpu(cell[2]);
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debug("irq_info %d: b.d.f %x.%x.%x INT%c PIRQ%c\n",
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i, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
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PCI_FUNC(pr.bdf), 'A' + pr.pin - 1,
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'A' + pr.pirq);
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fill_irq_info(&slot, &irq_entries, PCI_BUS(pr.bdf),
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PCI_DEV(pr.bdf), PCI_FUNC(pr.bdf),
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pr.pin, pr.pirq);
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cell += sizeof(struct pirq_routing) / sizeof(u32);
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}
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rt->size = irq_entries * sizeof(struct irq_info) + 32;
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pirq_routing_table = rt;
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return 0;
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}
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void pirq_init(void)
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{
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cpu_irq_init();
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if (create_pirq_routing_table()) {
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debug("Failed to create pirq routing table\n");
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} else {
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/* Route PIRQ */
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pirq_route_irqs(pirq_routing_table->slots,
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get_irq_slot_count(pirq_routing_table));
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}
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}
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u32 write_pirq_routing_table(u32 addr)
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{
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if (!pirq_routing_table)
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return addr;
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return copy_pirq_routing_table(addr, pirq_routing_table);
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}
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